• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.12
• /
• pp.210-216
• /
• 2014

In this paper, it was proposed to develop front and rear image monitoring system for vehicle that help a driver to cope with urgent situation about a dangerous element. When parking a vehicle, the risk factors to be formed by the dead zone can be resolved by using anterior and posterior cameras of the vehicle. In embedded system environment, a SoC(System on Chip) and two high-resolution CMOS (Complementary metal-oxide-semiconductor) image sensors were used to transfer two high-resolution image data through he TCP/ IP-based network. To transfer image data through he TCP/ IP-based network, the images received by two cameras were compressed by using H.264 and they were transmitted with wireless method(Wi-Fi) by using real-time transport protocol (Real-time Transport Protocol). Transmission loss, transmission delay and transmission limit were solved in wireless (Wi-Fi) environment and the bit-rate of two image data compressed by H.264 was adjusted. And the system for the optimal transmission in wireless (Wi-Fi) environment was materialized and experimented.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.3
• /
• pp.169-181
• /
• 2011

In this present paper, a comprehensive drain current model incorporating the effects of channel length modulation has been presented for multi-layered gate material engineered trapezoidal recessed channel (MLGME-TRC) MOSFET and the expression for linearity performance metrics, i.e. higher order transconductance coefficients: $g_{m1}$, $g_{m2}$, $g_{m3}$, and figure-of-merit (FOM) metrics; $V_{IP2}$, $V_{IP3}$, IIP3 and 1-dB compression point, has been obtained. It is shown that, the incorporation of multi-layered architecture on gate material engineered trapezoidal recessed channel (GME-TRC) MOSFET leads to improved linearity performance in comparison to its conventional counterparts trapezoidal recessed channel (TRC) and rectangular recessed channel (RRC) MOSFETs, proving its efficiency for low-noise applications and future ULSI production. The impact of various structural parameters such as variation of work function, substrate doping and source/drain junction depth ($X_j$) or negative junction depth (NJD) have been examined for GME-TRC MOSFET and compared its effectiveness with MLGME-TRC MOSFET. The results obtained from proposed model are verified with simulated and experimental results. A good agreement between the results is obtained, thus validating the model.

• Journal of IKEEE
• /
• v.20 no.4
• /
• pp.428-431
• /
• 2016

Power semiconductor devices had been producted with bipolar only processes, but Bipolar-CMOS-DMOS(BCD) processes have been adapted recently to fabricate these devices since most foundry companies have provided BCD processes instead of Bipolar only processes. In this study, Regulator and OP Amp are used as most popular design IPs and BCD processes for the designing are converted from bipolar only processes. Power Switching Sensor(PSS) ICs are designed specifically and fabricated on a silicon chip. The operation results of the packaged chip show the good matching with test results of the simulation.

• Proceedings of the KIEE Conference
• /
• 2000.07d
• /
• pp.2904-2906
• /
• 2000

본 논문에서는 반도체 제조 공정에서 장비와 호스트간에 통신을 할 수 있는 SECS(SEMI Equipment Communications Standard) 프로토를의 개발을 제안한다. SECS 프로토콜은 메시지 전송을 위한 헤더 부분을 정의하는 SECS-I 프로토콜과 메시지 내용을 정의하는 SECS-II 프로토콜로 나뉘어지는데, RS232 시리얼 통신을 하는 SECS-I 프로토콜 대신에 이더넷(ethernet)을 통해 TCP/IP 통신을 할 수 있는 HSMS 프로토콜을 구현하고자 한다. HSMS(High-speed SECS Message Services)프로토콜은 SECS-I과 마찬가지로 SECS-II 메시지 내용을 전송 할 수 있도록 10바이트 크기의 헤더로 정의된다. HSMS 프로토콜 통신은 TCP/IP를 기반으로 하기 때문에 SECS 메시지 전송을 위한 통신 선로를 설정하기 위해 소켓 API를 응용하고 항상 통신 대기상태를 유지하기 위해 데몬(daemon) 형태로 구성한다. 실제 메시지 내용을 정의하고 있는 SECS-II 프로토콜은 데이터 인덱스 테이블과 표준에 정의된 형식에 맞게 파일형태나 DLL(Dynamic Link Library)형태로 구성하고 프로세스 프로그램(process program)을 수행하기 위해 SECS 프로토콜 표준에서 정의하는 SML(SECS Message Language)형식으로 변환 할 수 있는 스크립트 변환기(script translator)를 구현한다. 또한 HSMS 프로토콜이 전송할 SECS-II 메시지를 저장하기 위한 파라미터를 정의하고 실제 통신을 위한 테스트 베드를 위한 응용 프로그램을 제작한다

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.11 no.2
• /
• pp.88-94
• /
• 2011

In this paper, we design a 1-kb OTP (Onetime programmable) memory IP in consideration of BCD process based EM (Electro-migration) and resistance variations of eFuse. We propose a method of precharging BL to VSS before activation of RWL (Read word-line) and an optimized design of read NMOS transistor to reduce read current through a non-programmed cell. Also, we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse. Peak current through the non-programmed eFuse is reduced from 728 ${\mu}A$ to 61 ${\mu}A$ when a simulation is done in the read mode. Furthermore, BL (Bit-line) sensing is possible even if sensed resistance of eFuse has fallen by about 9 $k{\Omega}$ in a wafer read test through a variable pull-up load resistance of BL S/A (Sense amplifier).

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.2 no.2
• /
• pp.132-140
• /
• 2002

This paper presents an ARM-based SOC bus transaction verification IP and the usage experiences in SOC designs. The verification IP is an AMBA AHB protocol checker, which captures legal AHB transactions in FSM-style signal sequence checking routines. This checker can be considered as a reusable verification IP since it does not change unless the bus protocol changes. Our AHB protocol checker is designed to be scalable to any number of AHB masters and reusable for various AMBA-based SOC designs. The keys to the scalability and the reusability are Object-Oriented Programming (OOP), virtual port, and bind operation. This paper describes how OOP, virtual port, and bind features are used to implement AHB protocol checker. Using the AHB protocol checker, an AHB simulation monitor is constructed. The monitor checks the legal bus arbitration and detects the first cycle of an AHB transaction. Then it calls AHB protocol checker to check the expected AHB signal sequences. We integrate the AHB bus monitor into Verilog simulation environment to replace time-consuming visual waveform inspection, and it allows us to find design bugs quickly. This paper also discusses AMBA AHB bus transaction coverage metrics and AHB transaction coverage analysis. Test programs for five AHB masters of an SOC, four channel DMAs and a host interface unit are executed and transaction coverage for DMA verification is collected during simulation. These coverage results can be used to determine the weak point of test programs in terms of the number of bus transactions occurred and guide to improve the quality of the test programs. Also, the coverage results can be used to obtain bus utilization statistics since the bus cycles occupied by each AHB master can be obtained.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.12 no.2
• /
• pp.117-126
• /
• 2012

This paper provides a method for compression transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively

• Proceedings of the Korea Information Processing Society Conference
• /
• 2006.05a
• /
• pp.1175-1178
• /
• 2006

반도체 공정 자동화를 위해 SEMI에서 제창한 표준 규약인 SECS Protocol은 메시지 전송을 위한 규약인 SECS-I과 HSMS, 실제 통신되는 메시지에 대한 규약인 SECS-II로 구성된다. 하지만 SECS-I에서는 통신속도가 느리고, 근거리 통신만 가능하고, 호스트 컴퓨터와 설비간의 연결이 1:1로 이루어져야 하는 등 여러 가지 문제점도 있고 요즘에는 TCP/IP 기반의 HSMS Protocol 장비가 나오기 때문에 SECS-I을 HSMS로 변환시켜 주는 장치가 필요하다. 본 논문에서는 SECS-I 지원용으로 제작된 설비라도 HSMS를 지원할 수 있도록 하여 HSMS가 갖는 여러 가지 장점을 갖도록 하는 SECS-I/HSMS 변환방법에 관해 살펴본다.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2017.04a
• /
• pp.567-570
• /
• 2017

산업공정에서 공정 정보처리의 극대화를 위하여 PLC, 로봇 등의 여러 프로그램식 단위제어기기가 네트워크로 연결되어 운영되고 있다. 대부분이 RS232C와 고유 장비의 전송절차에 의해 수행되어 왔지만, ISO 등에서는 반도체공정에 적용을 위한 SECS에 대한 프로토콜을 표준화하였다. 본 연구는 반도체 스퍼터 공정에 PLC, 로봇, 반송장치의 연결에 SECS-II를 적용하고, HSMS를 활용하여 TCP/IP와 Host를 연결하여 계층구조의 네트워크를 운영하였다. 전송 메세지 type을 stream과 function으로 나누어 송수신 확인과 데이터 전송절차를 설정하여 공정이 정상적으로 운영됨을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.3
• /
• pp.345-355
• /
• 2014

Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficient parallel scan test technique is introduced to minimize the test application time. Multiple scan enable signals are adopted to implement scan architecture to achieve optimal test application time for the test patterns scheduled for concurrent scan test. Experimental results show that testing times are considerably reduced with little area overhead.