• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.8
• /
• pp.73-81
• /
• 2012

In this paper, a novel phase locked loop has been proposed using an analog band-selection loop. When the PLL is out-lock, the PLL has a fasting locking characteristic with the analog band-selection loop. When the PLL is near in-lock, the bandwidth becomes narrow with the fine loop. A frequency voltage converter is introduced to improve a stability and a phase noise performance. The proposed PLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Journal of Astronomy and Space Sciences
• /
• v.27 no.2
• /
• pp.145-152
• /
• 2010

In this paper, we developed a local oscillator (LO) system of millimeter wave band receiver for radio astronomy observation. We measured the phase and amplitude drift stability of this LO system. The voltage control oscillator (VCO) of this LO system use the 3 mm band Gunn oscillator. We developed the digital phase locked loop (DPLL) module for the LO PLL function that can be computer-controlled. To verify the performance, we measured the output frequency/power and the phase/amplitude drift stability of the developed module and the commercial PLL module, respectively. We show the good performance of the LO system based on the developed PLL module from the measured data analysis. The test results and discussion will be useful tutorial reference to design the LO system for very long baseline interferometry (VLBI) receiver and single dish radio astronomy receiver at the 3 mm frequency band.

• Proceedings of the KIPE Conference
• /
• 2004.07b
• /
• pp.583-586
• /
• 2004

A typical method to control the single-phase power converter system is to utilize the zero-crossing PLL. However, this method is vulnerable to the voltage disturbance and affects the performance of controller This paper proposes a new single-phase PLL system that is composed of the adaptive linear combiner and the PI control. The operational principle was analyzed through theoretical approach and the performance was verified through simulations with MATLAB. The proposed PLL system shows rapidness and robustness in control under the voltage disturbances such as the sag, harmonics, and phase jump.

• Journal of Power Electronics
• /
• v.15 no.4
• /
• pp.1085-1092
• /
• 2015

In this paper, the expressions of the estimated information of a single-phase enhanced phase-locked loop (EPLL), when input signal contains harmonics and a DC offset while the fundamental component takes step changes, are derived. The theoretical analysis results indicate that in the estimated information, the n^th-order harmonics cause n+1^th-order periodic ripples, and the DC offset causes a periodic ripple at the fundamental frequency. Step changes of the amplitude, phase angle and frequency of the fundamental component cause a transient periodic ripple at twice the frequency. These periodic ripples deteriorate the performance of the EPLL. A hybrid filter based EPLL (HF-EPLL) is proposed to eliminate these periodic ripples. A delay signal cancellation filter is set at the input of the EPLL to cancel the DC offset and even-order harmonics. A sliding Goertzel transform-based filter is introduced into the amplitude estimation loop and frequency estimation loop to eliminate the periodic ripples caused by the residual input odd-order harmonics and step change of the input fundamental component. The parameter design rules of the two filters are discussed in detail. Experimental waveforms of both the conventional EPLL and the proposed HF-EPLL are given and compared with each other to verify the theoretical analysis and advantages of the proposed HF-EPLL.

• Korean Journal of Optics and Photonics
• /
• v.4 no.3
• /
• pp.330-337
• /
• 1993

Figure '8' type, passively-mode-locked erbium-doped-fiber ring laser was developed, incorporating a nonlinear loop mirror. Transmittance of the loop mirror was found to be dependent on the incident light intensity due to the non-reciprocal nonlinear phase shift, which enables the passive mode locking of the laser. Self-starting of stable mode locking was possible with only controlling the polarization controllers inside the cavity without any help of external perturbation or modulation. The mode-locked output pulse shape was discussed in relation with the transmission characteristics of nonlinear loop mirror.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
• /
• v.13 no.7
• /
• pp.649-656
• /
• 2002

This paper addresses the phase noise analysis of high-speed DH-PLL(Digital Hybrid Phase-Locked Loops) frequency synthesizer. Because of the additional quantization noise of D/A converter in DH-PLL, the phase noise of DH-PLL is increased than the conventional PLL. Three kinds of noise sources such as reference input, D/A converter, and VCO(Voltage Controlled Oscillator) are considered to analyze the phase noise. It largely depends on the closed loop bandwidth and frequency synthesis division ratio(N) so that we can decide the optimal closed loop bandwidth to minimize the phase noise of DH-PLL. It is shown that the simulation results closely match with the results of analytical approach.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.07b
• /
• pp.1132-1135
• /
• 2002

In this paper, we propose a phase-locked loop (PLL) with dual loops in which advantages of both loops can be combined. Frequency-locked loop (FLL) which is composed of two frequency-to-voltage converters (FVC) and an amplifier makes the frequency synchronize very fast and output signal is synchronized in phase with the input reference signal by charge pump PLL. This structure can improve the trade-off between acquisition behavior and locked behavior.

• Journal of Power Electronics
• /
• v.13 no.2
• /
• pp.322-328
• /
• 2013

This paper presents a modified Current Source Parallel Resonant Push-pull Inverter (CSPRPI) for single phase induction heating applications. One of the most important problems associated with current source parallel resonant inverters is achieving ZVS in transient intervals. This paper shows that a CSPRPI with the integral cycle control method has dynamic ZVS. According to this method, it is the Phase Locked Loop (PLL) circuit that tracks the switching frequency. The advantages of this technique are a higher efficiency, a smaller package size and a low EMI in comparison with similar topologies. Additionally, the proposed modification results in a low THD of the ac-line current. It has been measured as less than %2. To show the validity of the proposed method, a laboratory prototype is implemented with an operating frequency of 80 kHz and an output power of 400 W. The experimental results confirm the validity of the proposed single phase induction heating system.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.14 no.2
• /
• pp.198-201
• /
• 2014

The phase frequency detector (PFD) is one of the most important building blocks of a phase locked Loop (PLL). Due to blind-zone problem, the detection range of the PFD is low. The blind zone of a PFD directly depends upon the reset time of the PFD and the pre-charge time of the internal nodes of the PFD. Taking these two parameters into consideration, a PFD is designed to achieve a small blind zone closer to the limit imposed by process-voltage-temperature variations. In this paper an enhanced architecture is proposed for dynamic logic PFD to minimize the blind-zone problem. The techniques used are inverter sizing, transistor reordering and use of pre-charge transistors. The PFD is implemented in 180 nm technology with supply voltage of 1.8 V.

• ETRI Journal
• /
• v.34 no.4
• /
• pp.518-526
• /
• 2012

This paper proposes LC voltage-controlled oscillator (VCO) phase-locked loop (PLL) and ring-VCO PLL topologies with low-phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer-resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out-band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65-nm or 45-nm process. The measured results of the LC-VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of -118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring-VCO PLL shows a phase noise of -95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply.