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http://dx.doi.org/10.4218/etrij.12.0111.0417

A Low-Spur CMOS PLL Using Differential Compensation Scheme  

Yun, Seok-Ju (Convergence Components & Materials Research Laboratory, ETRI, Samsung Electronics)
Kim, Kwi-Dong (Convergence Components & Materials Research Laboratory, ETRI)
Kwon, Jong-Kee (Convergence Components & Materials Research Laboratory, ETRI)
Publication Information
ETRI Journal / v.34, no.4, 2012 , pp. 518-526 More about this Journal
Abstract
This paper proposes LC voltage-controlled oscillator (VCO) phase-locked loop (PLL) and ring-VCO PLL topologies with low-phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer-resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out-band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65-nm or 45-nm process. The measured results of the LC-VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of -118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring-VCO PLL shows a phase noise of -95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply.
Keywords
Phase-locked loop (PLL); differentially-tuned; CMOS; voltage-controlled oscillator (VCO); spur rejection; transformer; integrated circuit design;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
Times Cited By Web Of Science : 0  (Related Records In Web of Science)
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