JSTS:Journal of Semiconductor Technology and Science

The Institute of Electronics and Information Engineers (대한전자공학회)
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An Enhanced Architecture of CMOS Phase Frequency Detector to Increase the Detection Range

  • Thomas, Aby (Department of ECE, PSG College of Technology) ;
  • Vanathi, P.T. (Department of ECE, PSG College of Technology)
  • Received : 2013.08.26
  • Accepted : 2014.03.08
  • Published : 2014.04.30
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Abstract

The phase frequency detector (PFD) is one of the most important building blocks of a phase locked Loop (PLL). Due to blind-zone problem, the detection range of the PFD is low. The blind zone of a PFD directly depends upon the reset time of the PFD and the pre-charge time of the internal nodes of the PFD. Taking these two parameters into consideration, a PFD is designed to achieve a small blind zone closer to the limit imposed by process-voltage-temperature variations. In this paper an enhanced architecture is proposed for dynamic logic PFD to minimize the blind-zone problem. The techniques used are inverter sizing, transistor reordering and use of pre-charge transistors. The PFD is implemented in 180 nm technology with supply voltage of 1.8 V.

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References

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