ETRI Journal

  • 제34권4호
  • /
  • Pages.518-526
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  • 2012
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  • 1225-6463(pISSN)
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  • 2233-7326(eISSN)
한국전자통신연구원 (Electronics and Telecommunications Research Institute)
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A Low-Spur CMOS PLL Using Differential Compensation Scheme

  • Yun, Seok-Ju (Convergence Components & Materials Research Laboratory, ETRI, Samsung Electronics) ;
  • Kim, Kwi-Dong (Convergence Components & Materials Research Laboratory, ETRI) ;
  • Kwon, Jong-Kee (Convergence Components & Materials Research Laboratory, ETRI)
  • 투고 : 2011.06.30
  • 심사 : 2012.04.12
  • 발행 : 2012.08.30
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초록

This paper proposes LC voltage-controlled oscillator (VCO) phase-locked loop (PLL) and ring-VCO PLL topologies with low-phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer-resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out-band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65-nm or 45-nm process. The measured results of the LC-VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of -118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring-VCO PLL shows a phase noise of -95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply.

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참고문헌

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피인용 문헌

  1. A 3.8-GHz highly linear LC-VCO without a varactor device vol.10, pp.5, 2012, https://doi.org/10.1587/elex.10.20130038