Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference (한국전기전자재료학회:학술대회논문집)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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A Study on the Optimum Design of Fast-Lock PLL using FLL

FLL을 이용하여 Lock을 가속시킨 PLL의 최적 설계에 관한 연구

  • 강경 (고려대학교 전기공학과) ;
  • 박윤식 (고려대학교 전기공학과) ;
  • 박재범 (고려대학교 전기공학과) ;
  • 우영신 (고려대학교 전기공학과) ;
  • 성만영 (고려대학교 전기공학과)
  • Published : 2002.07.08
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Abstract

In this paper, we propose a phase-locked loop (PLL) with dual loops in which advantages of both loops can be combined. Frequency-locked loop (FLL) which is composed of two frequency-to-voltage converters (FVC) and an amplifier makes the frequency synchronize very fast and output signal is synchronized in phase with the input reference signal by charge pump PLL. This structure can improve the trade-off between acquisition behavior and locked behavior.

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