• 한국정보통신학회논문지
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• 제10권8호
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• pp.1465-1470
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• 2006

본 논문에서는 단거리 무선 통신의 새로운 국제 표준으로 부상하고 있는 2.4 GHz ZigBee 응용을 위한 저전력 CMOS LNA(Low Noise Amplifier)를 설계하였다. 제안한 구조는 전류 재사용 기법을 이용한 2단 cascade구조이며 회로의 설계에서 TSMC $0.18{\mu}m$ CMOS 공정을 사용하였다. 전류 재사용단은 두 단의 증폭기 전류를 공유함으로써 LNA의 전력 소모를 적게 하는 효과를 얻을 수 있다. 본 논문에서는 LNA설계 과정을 소개하고 ADS(Advanced Design System)를 이용한 모의실험 결과를 제시하여 검증하였다. 모의실험 결과, 1.0V의 전압이 인가될 때 1.38mW의 매우 낮은 전력 소모를 확인하였으며 이는 지금까지 발표된 LNA 중 가장 낮은 값이다. 또한 13.83dB의 최대 이득, -20.37dB의 입력 반사 손실, -22.48dB의 출력 반사 손실 그리 고 1.13dB의 최소 잡음 지수를 보였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.426-432
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• 2012

A fully-integrated low power K-band radar transceiver in 130 nm CMOS process is presented. It consists of a low-noise amplifier (LNA), a down-conversion mixer, a power amplifier (PA), and a frequency synthesizer with injection locked buffer for driving mixer and PA. The receiver front-end provides a conversion gain of 19 dB. The LNA achieves a power gain of 15 dB and noise figure of 5.4 dB, and the PA has an output power of 9 dBm. The phase noise of VCO is -90 dBc/Hz at 1-MHz offset. The total dc power dissipation of the transceiver is 142 mW and the size of the chip is only $1.2{\times}1.4mm^2$.

• 한국지능시스템학회논문지
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• 제10권5호
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• pp.478-486
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• 2000

본 논문에서는 CMOS 디지털 회로상의 플립플롭의 위치를 이동시키는 리타이밍 변환에 유전자 알고리즘을 적용하여 회로의 최적 동작 속도를 유지하면서 전력의 소모를 줄일 수 있는 설계 방법을 제안한다. 제안된 설계 방법은 최적 속도를 구현하는 리타이밍 단계와 유전자 알고리즘이 적용되는 저전력 리타이밍의 두 단계로 이루어진다. 제안된 저전력 리타이밍 설계 도구를 예제 회로의 설계에 적용하고 설계된 회로의 성능을 Synopsys시의 Design Analyzer로 평가한 결과, 임계 경로 지연은 약 30~50% 가량 감소하였으며 동적 전력 소모는 약 1.4~18.4% 가량 감소함을 관찰하였다.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 2009년도 IWAIT
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• pp.512-515
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• 2009

A 90-nm CMOS motion estimation (ME) processor was developed by employing dynamic voltage and frequency scaling (DVFS) to greatly reduce the dynamic power. To make full use of the advantages of DVFS, a fast ME algorithm and a small on-chip DC/DC converter were also developed. The fast ME algorithm can adaptively predict the optimum supply voltage ($V_D$) and the optimum clock frequency ($f_c$) before each block matching process starts. Power dissipation of the ME processor, which contained an absolute difference accumulator as well as the on-chip DC/DC converter and DVFS controller, was reduced to $31.5{\mu}W$, which was only 2.8% that of a conventional ME processor.

• 대한전자공학회논문지SD
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• 제41권1호
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• pp.81-90
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• 2004

유한상태기의 상태할당은 이로부터 구현되는 순차회로의 속도, 면적, 테스팅 및 소비전력에 큰 영향을 미친다. 본 논문에서는 상태변수 그룹들 사이에 상호 의존성(dependency)을 최소화하여 테스팅 및 전력소모를 개선하기 위한 m-블록 분할을 이용한 새로운 상태할당 기술을 소개한다. m-블록 분할 알고리즘에 의해 상태도로부터 상태들을 그룹으로 나누어 상태변수의 상호의존성을 줄이고, 상태천이 확률에 의해 결정된 무게인자에 따라 상태간 상태변수의 변화를 최소로하는 코드를 할당하여 상태천이시 스위칭 횟수를 줄인다. 상태변수 의존성을 줄임으로써 순차회로 사이클이 줄어들어서 부분스캔 및 테스트 생성이 용이하게 되고, 상태변수간의 스위칭 횟수를 줄임으로써 소비전력이 줄어들게 든다. 즉, 본 상태할당 기술은 서로 상반 관계에 있는 테스팅과 저전력 문제를 동시에 해결할 수 있는 새로운 기술이다. 벤치마크 회로에 대한 실험결과 기존의 방법보다 고장점검도 및 소비전력이 현저히 개선되었음을 확인하였다.

• Journal of Electrical Engineering and Technology
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• 제4권4호
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• pp.559-565
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• 2009

Power dissipation during scan testing is becoming an important concern as design sizes and gate densities increase. The high switching activity of combinational circuits is an unnecessary operation in scan shift mode. In this paper, we present a novel architecture to reduce test power dissipation in combinational logic by blocking signal transitions at the logic inputs during scan shifting. We propose a unique architecture that uses dmuxed scan flip-flop (DSF) and transmission gate as an alternative to muxed scan flip-flop. The proposed method does not have problems with auto test pattern generation (ATPG) techniques such as test application time and computational complexity. Moreover, our elegant method improves performance degradation and large overhead in terms of area with blocking logic techniques. Experimental results on ITC99 benchmarks show that the proposed architecture can achieve an average improvement of 30.31% in switching activity compared to conventional scan methods. Additionally, the results of simulation with DSF indicate that the powerdelay product (PDP) and area overhead are improved by 28.9% and 15.6%, respectively, compared to existing blocking logic method.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.703-706
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• 1998

This paper presents an efficient substrate-bias generator(SBG)for low-power, high-density DRAM's The proposed SBG can supply stable voltage with switching the supply voltage of driving circuit, and it can substitude the small capacitance for the large capacitance. The charge pumping circuit of the SBG suffere no VT loss and is to be applicable to low-voltage DRAM's. Also it can reduce the power consumption to make VBB because of it's high pumping efficiency. Using biasing voltage with positive temperature coefficient, VBB level detecting circuit can detect constant value of VBB against temperature variation. VBB level during VBB maintaining period varies 0.19% and the power dissipation during this period is 0.16mw. Charge pumping circuit can make VBB level up to -1.47V using VCC-1.5V, and do charge pumping operation one and half faster than the conventional ones. The temperature dependency of the VBB level detecting circuit is 0.34%. Therefore the proposed SBG is expected to supply a stable VBB with less power consumption when it is used in low power DRAM's.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.114.6-114
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• 2001

According to expansion of wireless communication system and mobile device, interest has been growing in personal navigation system integrated with wireless system. In portable consumer electronics, such as cellular phones, GPS and PDA, one of major design factors is the power consumption. Solutions of reducing the power dissipation are low voltage, low system clock power management and so on. This paper develops a GPS receiver based on the advanced power management algorithm that achieves very low average power consumption. Both RF and DSP chips are powered down and reactivated only when the position fixing is required. In order to run, the developed includes the RTC calibration function and the fast reacquisition function using XMC (eXtended Multiple Correlator) ...

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2005년도 춘계학술발표대회
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• pp.863-866
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• 2005

Low-power design is one of the most important challenges encountered in maximizing battery life in portable devices as well as saving energy during system operation. In this paper we propose a low-power DCT (Discrete Cosine Transform) architecture using a modified Computation Sharing Multiplication (CSHM). The overall rate of power consume is reduced during DCT: the proposed architecture does not perform arithmetic operations on unnecessary bits during the Computation Sharing Multiplication calculations. Experimental results show that it is possible to reduce power dissipation up to about $7{\sim}8%$ without compromising the final DCT results. The proposed lowpower DCT architecture can be applied to consumer electronics as well as portable multimedia systems requiring high throughput and low-power.

• ETRI Journal
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• 제29권6호
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• pp.785-793
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• 2007

In this paper, we present an integrated rail-to-rail fully differential operational transconductance amplifier (OTA) working at low-supply voltages (1.5 V) with reduced power consumption and showing high DC gain. An embedded adaptive biasing circuit makes it possible to obtain low stand-by power dissipation (lower than 0.17 mW in the rail-to-rail version), while the high DC gain (over 78 dB) is ensured by positive feedback. The circuit, fabricated in a standard CMOS integrated technology (AMS 0.35 ${\mu}m$), presents a 37 V/${\mu}s$ slew-rate for a capacitive load of 15 pF. Experimental results and high values of two quality factors, or figures of merit, show the validity of the proposed OTA, when compared with other OTA configurations.