Proceedings of the Korea Information Processing Society Conference (한국정보처리학회:학술대회논문집)

  • 2005.05a
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  • Pages.863-866
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  • 2005
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  • 2005-0011(pISSN)
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  • 2671-7298(eISSN)
Korea Information Processing Society (한국정보처리학회)
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Low-Power DCT Architecture by Minimizing Switching Activity

스위칭 엑티비티를 최소화한 저전력 DCT 아키텍쳐 구현

  • Kim, San (Dept. of Electrical and Electronic Engineering, Yonsei University) ;
  • Park, Jong-Su (Dept. of Electrical and Electronic Engineering, Yonsei University) ;
  • Lee, Yong-Surk (Dept. of Electrical and Electronic Engineering, Yonsei University)
  • 김산 (연세대학교 전기전자공학과) ;
  • 박종수 (연세대학교 전기전자공학과) ;
  • 이용석 (연세대학교 전기전자공학과)
  • Published : 2005.05.13
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Abstract

Low-power design is one of the most important challenges encountered in maximizing battery life in portable devices as well as saving energy during system operation. In this paper we propose a low-power DCT (Discrete Cosine Transform) architecture using a modified Computation Sharing Multiplication (CSHM). The overall rate of power consume is reduced during DCT: the proposed architecture does not perform arithmetic operations on unnecessary bits during the Computation Sharing Multiplication calculations. Experimental results show that it is possible to reduce power dissipation up to about $7{\sim}8%$ without compromising the final DCT results. The proposed lowpower DCT architecture can be applied to consumer electronics as well as portable multimedia systems requiring high throughput and low-power.

Keywords