Browse > Article

Development of Optimized State Assignment Technique for Testing and Low Power  

Cho Sangwook (Dept. of Computer Science & Engineering, Hanyang University)
Yi Hyunbean (Dept. of Computer Science & Engineering, Hanyang University)
Park Sungju (Dept. of Electrical Engineering Computer Science, Hanyang University)
Publication Information
Abstract
The state assignment for a finite state machine greatly affects the delay, area, power dissipation, and testabilities of the sequential circuits. In order to improve the testabilities and power consumption, a new state assignment technique . based on m-block partition is introduced in this paper. By the m-block partition algorithm, the dependencies among groups of state variables are minimized and switching activity is further reduced by assigning the codes of the states in the same group considering the state transition probability among the states. In the sequel the length and number of feedback cycles are reduced with minimal switching activity on state variables. It is inherently contradictory problem to optimize the testability and power consumption simultaneously, however our new state assignment technique is able to achieve high fault coverage with less number of scan nfp flops by reducing the number of feedback cycles while the power consumption is kept low upon the low switching activities among state variables. Experiment shows drastic improvement in testabilities and power dissipation for benchmark circuits.
Keywords
scan design; low power design; state assignment; m-block partition; partition pairs;
Citations & Related Records
연도 인용수 순위
  • Reference
1 R. K. Brayton, G. D. Hatchel, C. T. McMullen, and A. L. Sangiovanni-Vincentelli, Logic Minimization Algorithms for VLSI Synthesis, Norwell, MA: Kluwer Academic, 1984
2 Chiusano S, Corno F, Prinetto P, Rebaudengo M, Sonza Reorda M, 'Guaranteeing testability in re-encoding for low power,' Test Symposium (ATS '97) Proceedings, Sixth Asian , pp. 30-35, 1997   DOI
3 K. T. Cheng, and V. D. Agrawal, 'Design of Sequential Machines for Efficient Test Generation,' in Proc. of ICCAD, pp. 358-361, 1989   DOI
4 Z. Kohavi, Switching and Finite Automata Theory, McGraw-Hill, 1978
5 T. Villa et al., Synthesis of FSMs: Logic Optimization. New York: Kluwer Academic, 1997
6 L.Benini and G. De. Micheli, 'State assignment for loww power dissipation', IEEE Journal of Solid-State Circuits, vol. 30. March 1995   DOI   ScienceOn
7 구경회 and 조경록, '상태천이확률을 이용한 비동기 회로의 저전력 상태할당 알고리즘', 전자공학회 논문지 1999년 4월 제 36 권 C 편 제 4 호
8 G.D. Hachtel, M. Hermida, A. Pardo, M. Pon-cino, F. Somenzi, 'Re-Encoding Sequential Cir-cuits to Reduce Power Dissipation', proc. IEEE/ACM Intl. Conf. on CAD, pp. 70-73, 1994
9 E. Olson, S.M. Kang, 'Low-Power State Assignment for Finite State Machines', proc. IEEE Intl. Workshop on Low Power Design, pp. 63-68, April 1995
10 C.-Y. Tsui, M. Pedram, C.-A. Chen, A.M. De-spain, 'Low Power State Assignment Targeting Two- and Multi-level Logic Implementations', proc. IEEE/ACM Intl. Conf. on CAD, pp.82-87, 1994
11 V. Veeramachaneni, A. Tyagi, S. Rajgopal, 'Re-encoding for Low Power State Assignment of FSMs', proc. IEEE Intl. Symposium on Low Power Design, pp. 173-178, April 1995   DOI
12 Srikanth Rao M. and S. K. Nandy, 'Power Minimization Using Control Generated Clocks', proc. Design Automatin Conference, pp. 794-799, June 2000   DOI
13 S. Devadas et al., 'MUSTANG: State assignment of finite state machines targeting multi-level logic implementations', IEEE TCAD. Vol. 7, pp. 1290-1300, Dec. 1988   DOI   ScienceOn
14 T. Villa et al., 'Synthesis of FSMs: Logic Optimization. New York: Kluwer Academic', 1997
15 D. B. Armstrong, 'A Programmed Algorithm for Assigning Internal Codes to Sequential Machines' , IRE Trans. on Computers, Vol. EC-11, pp. 466-472, Aug. 1962   DOI
16 K. T. Cheng, and V. D. Agrawal, 'Design of Sequential Machines for Efficient Test Generation,', in Proc. of ICCAD, pp. 358-361, 1989   DOI
17 Surti P, Chao L.F, Tyagi A, 'Low power FSM design using Huffman-style encoding', European Design and Test Conference', ED&TC Proceedings, pp. 521-525, 1997   DOI
18 G. De Micheli, 'Symbolic Design of Combinational Sequential Logic Circuits Implemented by Two-level Logic Macros' , IEEE TCAD, Vol. CAD-5, pp. 597-616, Oct. 1986.1
19 E. Goldberg et al., 'Theory and Algorithms for Hypercube Embedding' ,IEEE Trans on CAD., Vol. 17, pp. 472-488, June 1998   DOI   ScienceOn
20 Saeyang Yang and Maciej J. Ciesielski, 'Optimum and Suboptimum Algorithms for Input Encoding and Its Relationship to Logic Minimization', IEEE Trans. on CAD., Vol 10. No. 1. pp. 4-12, Jan. 1991   DOI   ScienceOn
21 M. Abramovici et al., 'Digital Systems Testing and Testable Design', Computer Science Press, 1994
22 K. T. Cheng and V. D. Agrawal, 'A Partial Scan Method for Sequential Circuits with Feedback' , IEEE Trans. on Computers, Vol. 39, No.4, pp. 544-548, April 1990   DOI   ScienceOn