• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.7
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• pp.1657-1662
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• 2014

In this paper, the impact of substrate bias($V_{BS}$) on the zero capacitor RAM(Z-RAM) in n-channel junctionless multiple gate MOSFET(MuGFET) has been analyzed experimentally. Junctionless transistors with fin width of 50nm and 1 fin exhibits a memory window of 0.34V and a sensing margin of $1.8{\times}10^4$ at $V_{DS}=3.5V$ and $V_{BS}=0V$. As the positive $V_{BS}$ is applied, the memory window and sensing margin were improved due to an increase of impact ionization. When $V_{BS}$ is increased from 0V to 10V, not only the memory window is increased from 0.34V to 0.96V but also sensing margin is increased slightly. The sensitivity of memory window with different $V_{BS}$ in junctionless transistor was larger than that of inversion-mode transistor. A retention time of junctionless transistor is better than that of inversion-mode transistor due to low Gate Induced Drain Leakage(GIDL) current. To evaluate the device reliability of Z-RAM, the shifts in the Set/Reset voltages and current were measured.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.230-239
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• 2012

In this paper, we present the radio-frequency (RF) modeling for gate-all-around (GAA) junctionless (JL) MOSFETs with 30-nm channel length. The presented non-quasi-static (NQS) model has included the gate-bias-dependent components of the source and drain (S/D) resistances. RF characteristics of GAA junctionless MOSFETs have been obtained by 3-dimensional (3D) device simulation up to 1 THz. The modeling results were verified under bias conditions of linear region (VGS = 1 V, VDS = 0.5 V) and saturation region (VGS = VDS = 1 V). Under these conditions, the root-mean-square (RMS) modeling error of $Y_{22}$-parameters was calculated to be below 2.4%, which was reduced from a previous NQS modeling error of 10.2%.

• Journal of IKEEE
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• v.22 no.1
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• pp.74-79
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• 2018

We analyzed the relationship between center potential and subthreshold swing (SS) of Junctionless Cylindrical Surrounding Gate (JLCSG) and Junctionless Double Gate (JLDG) MOSFET. The SS was obtained using the analytical potential distribution and the center potential, and SSs were compared and investigated according to the change of channel dimension. As a result, we observed that the change in central potential distribution directly affects the SS. As the channel thickness and oxide thickness increased, the SS increased more sensitively in JLDG. Therefore, it was found that JLCSG structure is more effective to reduce the short channel effect of the nano MOSFET.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.789-794
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• 2017

Subthreshold current model is presented using analytical potential distribution of junctionless cylindrical surrounding-gate (CSG) MOSFET and threshold voltage shift is analyzed by this model. Junctionless CSG MOSFET is significantly outstanding for controllability of gate to carrier flow due to channel surrounded by gate. Poisson's equation is solved using parabolic potential distribution, and subthreshold current model is suggested by center potential distribution derived. Threshold voltage is defined as gate voltage corresponding to subthreshold current of $0.1{\mu}A$, and compared with result of two dimensional simulation. Since results between this model and 2D simulation are good agreement, threshold voltage shift is investigated for channel dimension and doping concentration of junctionless CSG MOSFET. As a result, threshold voltage shift increases for large channel radius and oxide thickness. It is resultingly shown that threshold voltage increases for the large difference of doping concentrations between source/drain and channel.

• Journal of Electrical Engineering and Technology
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• v.8 no.6
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• pp.1497-1502
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• 2013

Recently, the junctionless (JL) transistors realized by a single-type doping process have attracted attention instead of the conventional metal-oxide-semiconductor field-effect transistors (MOSFET). The JL transistor can overcome MOSFET's problems such as the thermal budget and short-channel effect. Thus, the JL transistor is considered as great alternative device for a next generation low standby power silicon system. In this paper, the JL FinFET was simulated with a three dimensional (3D) technology computer-aided design (TCAD) simulator and optimized for DC characteristics according to device dimension and doping concentration. The design variables were the fin width ($W_{fin}$), fin height ($H_{fin}$), and doping concentration ($D_{ch}$). After the optimization of DC characteristics, RF characteristics of JL FinFET were also extracted.

• Proceeding of EDISON Challenge
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• 2014.03a
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• pp.420-424
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• 2014

본 논문에서는 접합을 가지지 않는 Junctionless transistor (JLT)의 두께에 따른 특성 차이 및 기존의 MOSFET과의 특성 비교를 EDISON 시뮬레이터를 통해 확인을 하였다. JLT의 두께가 얇아짐에 따라 On/off 비율 측면에서 소자의 특성이 향상됨을 확인 하였으며, 기존 Inversion mode의 MOSFET과 비교하여 단 채널 효과 측면에서도 향상된 특성을 확인 할 수 있었다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.9
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• pp.1627-1634
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• 2017

In this work, a junctionless transistor with different film thickness of amorphous InGaZnO has been fabricated and it's instability has been analyzed with different film thickness under positive and negative gate stress as well as light illumination. It was found that the threshold voltage shift and the variation of drain current have been increased with decrease of film thickness under the condition of gate stress and light illumination. The reasons for the observed results have been explained by stretched-exponential model and device simulation. Due to the reduced carrier trapping time with decrease of film thickness, electrons and holes can be activated easily. Due to the increase of vertical channel electric field reaching the back interface with decrease of film thickness, more electrons and holes can be accumulated in back interface. When one decides the film thickness for the fabrication of junctionless transistor, the more significant device instability with decrease of film thickness should be consdered.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.1
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• pp.117-124
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• 2018

Junctionless amorphous InGaZnO thin film transistors with different film thickness have been fabricated. Their device performance parameters were extracted and gate oxide breakdown voltages were analyzed with different film thickness. The device performances were enhanced with increase of film thickness but the gate oxide breakdown voltages were decreased. The device performances were enhanced with increase of temperatures but the gate oxide breakdown voltages were decreased due to the increased drain current. The drain current under illumination was increased due to photo-excited electron-hole pair generation but the gate oxide breakdown voltages were decreased. The reason for decreased breakdown voltage with increase of film thickness, operation temperature and light intensity was due to the increased number of channel electrons and more injection into the gate oxide layer. One should decide the gate oxide thickness with considering the film thickness and operating temperature when one decides to replace the junctionless amorphous InGaZnO thin film transistors as BEOL transistors.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.159-165
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• 2016

Recently, active efforts are being made for future Si CMOS technology by various researches on emerging devices and materials. Capability of low power consumption becomes increasingly important criterion for advanced logic devices in extending the Si CMOS. In this work, a junctionless field-effect transistor (JLFET) with ultra-thin poly-Si (UTP) channel is designed aiming the sub-10-nm technology for low-power (LP) applications. A comparative study by device simulations has been performed for the devices with crystalline and polycrystalline Si channels, respectively, in order to demonstrate that the difference in their performances becomes smaller and eventually disappears as the 10-nm regime is reached. The UTP JLFET would be one of the strongest candidates for advanced logic technology, with various virtues of high-speed operation, low power consumption, and low-thermal-budget process integration.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.31 no.5
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• pp.278-282
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• 2018

We propose a SPICE model of drain-induced barrier lowering (DIBL) for a junctionless cylindrical surrounding gate (JLCSG) MOSFETs. To this end, the potential distribution in the channel is obtained via the Poisson equation, and the threshold voltage model is presented for the JLCSG MOSFET. In a JLCSG nano-structured MOSFET, a channel radius affects the carrier transfer as well as the channel length and oxide thickness; therefore, DIBL should be expressed as a function of channel length, channel radius, and oxide thickness. Consequently, it can be seen that DIBLs are proportional to the power of -3 for the channel length, 2 for the channel radius, 1 for the thickness of the oxide film, and the constant of proportionality is 18.5 when the SPICE parameter, the static feedback coefficient ${\eta}$, is between 0.2 and 1.0. In particular, as the channel radius and the oxide film thickness increase, the value of ${\eta}$ remains nearly constant.