• JSTS:Journal of Semiconductor Technology and Science
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• 제9권1호
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• pp.8-13
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• 2009

In this paper, discontinuous interconnect lines are modeled as a cascaded line composed of many uniform interconnect lines. The system functions of respective uniform interconnect lines are determined, followed by its time domain response. Since the time domain response expression is a transcendental form, the waveform expression is reconfigured as an approximated linear expression. The proposed model has less than 2% error in the delay estimation.

• 대한전자공학회논문지SD
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• 제37권6호
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• pp.50-56
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• 2000

초고주파에서 집적회로용 연결선(interconnect)에 PGS(Patterned Grouned Shield)를 적용하는 실험을 하였다. PGS는 신호선으로부터 비절연 실리콘 기판을 차폐시킴으로써 광대역에 걸쳐 전송선의 실리콘기판을 통한 전력손실을 크게 줄일 수 있음을 측정결과를 통해 보였다. 또한 PGS를 이용한 전송선의 특성을 분석하고 PGS가 전송선의 파장을 줄여주는 효과가 있음을 확인하였다.

• ETRI Journal
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• 제45권5호
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• pp.910-921
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• 2023

In this study, we designed a 6T-SRAM cell using 16-nm CMOS process and analyzed the performance in terms of read-speed latency. The temperaturedependent Cu and multilayered graphene nanoribbon (MLGNR)-based nanointerconnect materials is used throughout the circuit (primarily bit/bit-bars [red lines] and word lines [write lines]). Here, the read speed analysis is performed with four different chip operating temperatures (150K, 250K, 350K, and 450K) using both Cu and graphene nanoribbon (GNR) nano-interconnects with different interconnect lengths (from 10 ㎛ to 100 ㎛), for reading-0 and reading-1 operations. To execute the reading operation, the CMOS technology, that is, the16-nm PTM-HPC model, and the16-nm interconnect technology, that is, ITRS-13, are used in this application. The complete design is simulated using TSPICE simulation tools (by Mentor Graphics). The read speed latency increases rapidly as interconnect length increases for both Cu and GNR interconnects. However, the Cu interconnect has three to six times more latency than the GNR. In addition, we observe that the reading speed latency for the GNR interconnect is ~10.29 ns for wide temperature variations (150K to 450K), whereas the reading speed latency for the Cu interconnect varies between ~32 ns and 65 ns for the same temperature ranges. The above analysis is useful for the design of next generation, high-speed memories using different nano-interconnect materials.

• 대한전자공학회논문지SD
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• 제43권7호
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• pp.20-28
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• 2006

본 논문에서는 불규칙하고 복잡한 다층(multi-layer) RLC 배선에 대하여 TWA(Traveling-wave-based Waveform Approximation)을 기반으로 한 새로운 시그널 인테그러티 검증에 대한 방법을 제시한다. 실제 레이아웃 구조의 불규칙한 배선을 가상 직선 배선으로 변환하고 이를 TWA 기법을 사용하여 효율적으로 검증하였다. 여기서 제안된 방법은 3차원 구조에 대한 회로 모델을 사용한 일반적인 SPICE 시뮬레이션에 비하여 계산시간을 현저하게 단축시킬 수 있으며, 타이밍의 경우 5% 이내에서, 크로스톡의 경우 10% 이내에서 정확하다는 것을 보인다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권4호
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• pp.260-266
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• 2007

Analytical compact form models for the signal transients and crosstalk noise of inductive-effect-prominent multi-coupled RLC lines are developed. Capacitive and inductive coupling effects are investigated and formulated in terms of the equivalent transmission line model and transmission line parameters for fundamental modes. The signal transients and crosstalk noise expressions of two coupled lines are derived by using a waveform approximation technique. It is shown that the models have excellent agreement with SPICE simulation.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권6호
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• pp.594-607
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• 2013

A new efficient analytical eye-diagram determination technique for coupled interconnect lines is presented. Two coupled lines are decoupled into isolated eigen modes; bit blocks for coupled lines, which are defined as a block of consecutive bits, are then represented with decoupled modes. The crosstalk effects within the bit blocks are taken into account. Thereby, the crucial input bit patterns for the worst case eye-diagram determination are modeled mathematically, including inter-symbol interference (ISI). The proposed technique shows excellent agreement with the SPICE-based simulation. Furthermore, it is very computation-time-efficient in the order of magnitude, compared with the SPICE simulation, which requires numerous pseudo-random bit sequence (PRBS) input signals.

• JSTS:Journal of Semiconductor Technology and Science
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• 제11권1호
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• pp.15-22
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• 2011

Interconnect lines with inter-layer vias are experimentally characterized by using high-frequency S-parameter measurements. Test patterns are designed and fabricated using a package process. Then they are measured using Vector Network Analyzer (VNA) up to 25 GHz. Modeling a via as a circuit, its model parameters are determined. It is shown that the circuit model has excellent agreement with the measured S-parameters. The signal integrity of the lines with inter-layer vias is evaluated by using the developed circuit model. Thereby, it is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits.

• 대한전자공학회논문지SD
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• 제39권9호
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• pp.19-27
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• 2002

실리콘 기판가 교차하는 금속 선의 밑층 기하구조를 고려한 연결선로의 특성이 정교하게 고안된 패턴을 가지고 실험적으로 분석되었다. 이 작업에서, 여러 종류의 밑층 기하구조에 따른 전송선로을 위한 테스트 패턴들을 고안하였고, 신호 특성과 반응은 S-parameter 와 TDR을 통해 측정되었다. 사용된 패턴은 두 개의 알루미늄 선과 한 개의 텅스텐 선을 가지는 deep-submicron CMOS DRAM 기술을 가지고 설계되고 제작되었다. 패턴위에서 측정되 결과 분석으로부터, 라인 파라메터들 (특히 라인 커패시턴스와 저항) 과 그것들에 의한 신호 왜곡에 대한 밑층 구조에 의한 효과는 무시 할수 없음을 발견하였다. 그러한 결과는 고속 클럭과 데이터 라인 같은 글로벌 신호 선이나 패키지 리드의 스큐 발렌스의 심도있고 유용한 이해에 도움이 된다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권6호
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• pp.824-831
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• 2014

In this study, structural variations and overlay errors caused by multiple patterning lithography techniques to print narrow parallel metal interconnects are investigated. Resistance and capacitance parasitic of the six lines of parallel interconnects printed by double patterning lithography (DPL) and triple patterning lithography (TPL) are extracted from a field solver. Wide parameter variations both in DPL and TPL processes are analyzed to determine the impact on signal propagation. Simulations of 10% parameter variations in metal lines show delay variations up to 20% and 30% in DPL and TPL, respectively. Monte Carlo statistical analysis shows that the TPL process results in 21% larger standard variation in delay than the DPL process. Crosstalk simulations are conducted to analyze the dependency on the conditions of the neighboring wires. As expected, opposite signal transitions in the neighboring wires significantly degrade the speed of signal propagation, and the impact becomes larger in the C-worst metals patterned by the TPL process compared to those patterned by the DPL process. As a result, both DPL and TPL result in large variations in parasitic and delay. Therefore, an accurate understanding of variations in the interconnect parameters by multiple patterning lithography and adding proper margins in the circuit designs is necessary.

• 마이크로전자및패키징학회지
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• 제12권1호
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• pp.27-33
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• 2005

The effect of microstructure on alternating current-induced damage in 200 and 300 nm thick polycrystalline sputtered Cu lines on Si substrates has been investigated. Alternating currents were used to generate temperature cycles (with ranges from 100 to $300^{\circ}C$) and thermal strains (with ranges from 0.14 to $0.42\%$) in the Cu lines at a frequency of 10 kHz. Fatigue loading caused the development of severe surface roughness that was localized within individual grains which depends severely on grain orientations.