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Underlayer Geometry Effects on Interconnect Line Characteristics and Signal Integrity  

Wee, Jae-Kyung (Div. of Information and Electrics Eng., Hallym University)
Kim, Yong-Ju (Div. of Information and Electrics Eng., Hallym University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.39, no.9, 2002 , pp. 19-27 More about this Journal
Abstract
Characteristics of interconnect lines considering underlayer geometries of a silicon substrate and crossing metal lines are experimentally analyzed through elaborately devised patterns. In this work, test patterns for transmission lines having several kinds of underlayer geometries were devised, and the signal characteristics and responses are measured by S-parameter and time domain reflection meter (TDR). The patterns were designed and fabricated with a deep-submicron CMOS DRAM technology having 1 Tungsten and 2 Aluminum metals. From the analysis of measured results on the patterns, it is founded that the effects of underlayter line structures on line parameters (especially line capacitance and resistance) and signal distortions occurred from them cannot be negligible. The results provide useful and insightful understanding in the skew balance of package leads and global signal lines such as high-speed clock and data lines.
Keywords
interconnect; s-parameter; substrate effect; current return path;
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