JSTS:Journal of Semiconductor Technology and Science

  • 제11권1호
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  • Pages.15-22
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  • 2011
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  • 1598-1657(pISSN)
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  • 2233-4866(eISSN)
대한전자공학회 (The Institute of Electronics and Information Engineers)
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Experimental Characterization and Signal Integrity Verification of Interconnect Lines with Inter-layer Vias

  • Kim, Hye-Won (Dept. Electrical and Computer Engineering, Hanyang University) ;
  • Kim, Dong-Chul (Dept. Electrical and Computer Engineering, Hanyang University) ;
  • Eo, Yung-Seon (Dept. Electrical and Computer Engineering, Hanyang University)
  • 투고 : 2010.11.19
  • 심사 : 2011.02.07
  • 발행 : 2011.03.31
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초록

Interconnect lines with inter-layer vias are experimentally characterized by using high-frequency S-parameter measurements. Test patterns are designed and fabricated using a package process. Then they are measured using Vector Network Analyzer (VNA) up to 25 GHz. Modeling a via as a circuit, its model parameters are determined. It is shown that the circuit model has excellent agreement with the measured S-parameters. The signal integrity of the lines with inter-layer vias is evaluated by using the developed circuit model. Thereby, it is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits.

키워드

참고문헌

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피인용 문헌

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