• Journal of Sensor Science and Technology
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• v.31 no.3
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• pp.151-155
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• 2022

In this paper, we present a highly-sensitive gate/body-tied (GBT) metal-oxide semiconductor field-effect transistor (MOSFET)-type photodetector using multi-finger structure whose photocurrent increases in proportion to the number of fingers. The drain current that flows through a MOSFET using multi-finger structure is proportional to the number of fingers. This study intends to confirm that the photocurrent of a GBT MOSFET-type photodetector that uses the proposed multi-finger structure is larger than the photocurrent per unit area of the existing GBT MOSFET-type photodetectors. Analysis and measurement of a GBT MOSFET-type photodetector that utilizes a multi-finger structure confirmed that photocurrent increases in ratio to the number of fingers. In addition, the characteristics of the photocurrent in relation to the optical power were measured. In order to determine the influence of the incident the wavelength of light, the photocurrent was recorded as the incident the wavelength of light varied over a range of 405 to 980 nm. A highly-sensitive GBT MOSFET-type photodetector with multi-finger structure was designed and fabricated by using the Taiwan semiconductor manufacturing company (TSMC) complementary metal-oxide-semiconductor (CMOS) 0.18 um 1-poly 6-metal process and its characteristics have been measured.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.581-582
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• 2006

In this paper, we investigate three different types of multi-fingered layout nMOSFET devices with varying $W_f$(unit finger width) and $N_f$(number of finger). Using layout modification, we improve $f_T$(current gain cutoff frequency) value of 15GHz without scaling down, and moreover, we decrease $NF_{min}$(minimum noise figure) by 0.23dB at 5GHz. The RF noise can be reduced by increasing $f_T$, choosing proper finger width, and reducing the gate resistance. For the same total gate width using multi-fingered layout, the increase of finger width shows high $f_T$ due to the reduced parasitic capacitance. However, this does not result in low $NF_{min}$ since the gate resistance generating high thermal noise becomes larger under wider finger width. We can obtain good RF characteristics for MOSFETs by using a layout optimization technique.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.12
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• pp.59-65
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• 2014

Two input resistances converted from $S_{11}$-parameter and $Z_{11}$-parameter of MOSFETs with various gate finger numbers Nf were measured in low frequency region. The 1/Nf dependent input resistance from $S_{11}$-parameter exhibits much lower values than that from $Z_{11}$-parameter in the range of $Nf{\leq}64$. This 1/Nf dependence was theoretically verified by using Nf dependent nonlinear equation derived from a MOSFET equivalent circuit.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.10
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• pp.875-880
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• 2008

In this paper, we deal with the TLP evaluation results for GGNMOS in ESD protection device of conventional CMOS process. An evaluation parameter for GGNMOS is that repeatability evaluation for reference device($W/L=50\;{\mu}m1.0\;{\mu}m$) and following factors for design as gate width, number of finger, present or not for N+ gurad -ring, space of N-field region to contact and present or not for NLDD layer. The result of repeatability was showed uniformity of lower than 1 %. The result for design factor evaluation was ; 1) gate width leading to increase It2, 2) An increase o( finger number was raised current capability(It2), and 3) present of N+ gurad-ring was more effective than not them for current sink. Finally we suggest the optimized design conditions for GGNMOS in evaluated factor as ESD protection device of conventional CMOS process.

• Journal of electromagnetic engineering and science
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• v.13 no.2
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• pp.127-133
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• 2013

We examined the scaling effects of a number of gate_fingers (N) and gate_widths (w) on the high-frequency characteristics of $0.1-{\mu}m$ metamorphic high-electron-mobility transistors. Functional relationships of the extracted small-signal parameters with total gate widths ($w_t$) of different N were proposed. The cut-off frequency ($f_T$) showed an almost independent relationship with $w_t$; however, the maximum frequency of oscillation ($f_{max}$) exhibited a strong functional relationship of gate-resistance ($R_g$) influenced by both N and $w_t$. A greater $w_t$ produced a higher $f_{max}$; but, to maximize $f_{max}$ at a given $w_t$, to increase N was more efficient than to increase the single gate_width.

• Transactions on Electrical and Electronic Materials
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• v.12 no.6
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• pp.245-248
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• 2011

The scaling down of metal oxide semiconductor field-effect transistors (MOSFETs) for the last several years has contributed to the reduction of the scaling variables and device parameters as well as the operating voltage of the MOSFET. At the same time, the variation in the electrical characteristics of MOSFETs is one of the major issues that need to be solved. Especially because the issue with variation is magnified as the drive voltage is decreased. Therefore, this paper will focus on the variations between electrical characteristics and drain voltage. In order to do this, the test patterned multi-finger MOSFETs using 90-nm process is used to investigate the characteristic variations, such as the threshold voltage, DIBL, subthreshold swing, transconductance and mobility via parasitic resistance extraction method. These characteristics can be analyzed by varying the gate width and length, and the number of fingers. Through this modeling scheme, the characteristic variations of multi-finger MOSFETs can be analyzed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.6
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• pp.383-389
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• 2001

We report on the design, fabrication, and characterization of 0.35${\mu}{\textrm}{m}$-gate AIGaAs/InGaAs PHEMTs for millimeter-wane applications. The epi-wafer structures were designed using ATLAS for optimum DC and AC characteristics, 0.351m-gate AIGaAs/rnGaAs PHEMTs having different gate widths and number of fingers were fabricated using electron beam lithography Dependence of RF characteristics of PHEMT on gate finger with and number of gate fingers have been investigated. PHEMT haying two 0.35$\times$60${\mu}{\textrm}{m}$$^2$ gate fingers showed the knee voltage, pinch-off voltage, drain saturation current density, and maximum transconductance of 1.2V, -1.5V, 275㎃/mm, and 260.17㎳/mm, respectively. The PHEMT showed fT(equation omitted)(current gain cut-off frequency) of 45㎓ and fmax(maximum oscillation frequency) of 100㎓. S$_{21}$ and MAG of the PHEMT were 3.6dB and 11.15dB, respectively, at 35㎓

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.539-540
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• 2006

The dependence of cutoff frequency and maximum oscillation frequency of $0.13{\mu}m$ CMOS transistors on layout parameters such as the unit gate width and gate finger number is measured and analyzed in this paper. This information will be very useful for high performance RF IC design.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.12-15
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• 2000

In this paper, we have fabricated the PHEMT's with AlGaAs/InGaAs/GaAs and measured characteristics of DC and frequencies. The PHEMT's has a 0.35$\mu\textrm{m}$ gate length, gate width of 60$\mu\textrm{m}$ and 80$\mu\textrm{m}$, and fingers of 2 and 4. From the measurements results for the 60$\mu\textrm{m}$ ${\times}$ 2 PHEMT's, we obtained 1.2V of Vk, -3.5V of Vp, 46mA of Idss, 221mS/mmof gm, and 3.6dB of S$\sub$21/ gain, 45GHz of f$\sub$T,/ 100GHz of fmax. And, in case of 80$\mu\textrm{m}$ ${\times}$ 4 PHEMT's, we obtained 1.2V of Vk, -4.5V of Vp, 125mA of Idss, 198mS/mm of gm, and 2.0dB of S$\sub$21/ gain. 44GHz of f$\sub$T/, 70GHz of fmax at 35GHz frequency. Also, MAG are decreased as a number of finger are Increased.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.8-14
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• 2012

The device performances of n-channel MuGFET with different fin numbers and fin widths but the total effective channel width is constant have been characterized. Two kinds of Pi-gate devices with fin number=16, fin width=55nm, and fin number=14, fin width=80nm have been used in characterization. The threshold voltage, effective electron mobility, threshold voltage roll-off, inverse subthreshold slope, PBTI, hot carrier degradation, and drain breakdown voltage have been characterized. From the measured results, the short channel effects have been reduced for narrow fin width and large fin numbers. PBTI degradation was more significant in devices with large fin number and narrow fin width but hot carrier degradation was similar for both devices. The drain breakdown voltage was higher for devices with narrow fin width and large fin numbers. With considering the short channel effects and device degradation, the devices with narrow fin width and large fin numbers are desirable in the device layout of MuGFETs.