1 |
B. K. Joung, J. W. Kang, H. J. Hwang, S. Y. Kim, and O. K. Kwon, "Trade-off characteristic between gate length margin and hot carrier lifetime by considering ESD on NMOSFETs of submicron technology", Trans. EEM, Vol. 7, No. 1, p. 1, 2006
과학기술학회마을
DOI
ScienceOn
|
2 |
J. K. Keller, "Protection of MOS integrated circuits from destruction by electrostatic discharge", EOS/ESD Symposium Proc., 1980
|
3 |
Stephen G. Beebe, "Characterization, Modeling, and Design of ESD Protection Circuits", Technical report, Advanced micro devices, Sunnyvale, California, 1998
|
4 |
T. Smdes, R. M. D. A. Velghe, R. S. Ruth, and A. J. Huitsing, "The application of transmission line pulse testing for the ESD analysis of integrated circuits", Journal of Electrostatics 56, p. 399, 2002
DOI
ScienceOn
|
5 |
A. Stricker, D. Gloor, and W. Fichtner, "Layer optimization of an ESD protection n- MOSFET by simulation and measurement", in Proc. EOS/ESD Symp., p. 205, 1995
|
6 |
정민철, 윤지영, 유장우, 성만영, "ESD 보호를 위한 LVTSCR의 래치업 차폐회로", 한국전기전자재료학회 2005하계학술대회논문집, p. 178, 2005
|
7 |
S. Dabral and T. Maloney, "Basic ESD and I/O Design", John Wiley & Sons, Inc., p. 16, 1998
|
8 |
Steven H. Voldman, "ESD Physics and Devices", John Wiley & Sons, Ltd., p. 7, 2005
|