Transactions on Electrical and Electronic Materials

  • 제12권6호
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  • Pages.245-248
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  • 2011
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  • 1229-7607(pISSN)
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  • 2092-7592(eISSN)
한국전기전자재료학회 (The Korean Institute of Electrical and Electronic Material Engineers)
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Modeling Electrical Characteristics for Multi-Finger MOSFETs Based on Drain Voltage Variation

  • Kang, Min-Gu (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Yun, Il-Gu (Department of Electrical and Electronic Engineering, Yonsei University)
  • 투고 : 2011.08.22
  • 심사 : 2011.10.20
  • 발행 : 2011.12.25
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초록

The scaling down of metal oxide semiconductor field-effect transistors (MOSFETs) for the last several years has contributed to the reduction of the scaling variables and device parameters as well as the operating voltage of the MOSFET. At the same time, the variation in the electrical characteristics of MOSFETs is one of the major issues that need to be solved. Especially because the issue with variation is magnified as the drive voltage is decreased. Therefore, this paper will focus on the variations between electrical characteristics and drain voltage. In order to do this, the test patterned multi-finger MOSFETs using 90-nm process is used to investigate the characteristic variations, such as the threshold voltage, DIBL, subthreshold swing, transconductance and mobility via parasitic resistance extraction method. These characteristics can be analyzed by varying the gate width and length, and the number of fingers. Through this modeling scheme, the characteristic variations of multi-finger MOSFETs can be analyzed.

키워드

참고문헌

  1. International Technology Roadmap for Semiconductors 2009, design chapter. Retrieved from http://www.itrs.net/links/2009itrs/home2009.htm.
  2. M. Fathipour, F. Kohani, and Z. Ahangari, Conference on Optoelectronic and Microelectronic Materials and Devices (Sydney, SA 2008 Jul. 28-Aug. 1) p. 136. [http://dx.doi.org/10.1109/COMMAD.2008.4802110].
  3. C. H. Park, J. H. Kang, S. O. Jung, and I. Yun, IEEE International Conference on Electron Devices and Solid-State Circuits (Hong Kong 2008 Dec. 8-10) p. 1. [http://dx.doi.org/10.1109/EDSSC.2008.4760677].
  4. S. Luan, J. Appl. Phys. 72, 766 (1992) [http://dx.doi.org/10.1063/1.351809].
  5. Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices (Cambridge University Press, Cambrige, UK, 1998) p. 140.
  6. B. S. Doyle, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kavalieros, T. Linton, A. Murthy, R. Rios, and R. Chau, IEEE Electron Device Lett. 24, 263 (2003) [http://dx.doi.org/10.1109/LED.2003.810888].
  7. D. Helms, E. Schmidt, and W. Nebel, Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation. Lecture Notes in Computer Science Vol. 3254, eds. [7] E. Macii, V. Paliouras, and O. Koufopavlou (Springer Berlin, Heidelberg, Germany, 2004) p. 17 [http://dx.doi.org/10.1007/978-3-540-30205-6_5].
  8. M. A. Abdi, F. Djeffal, D. Arar, and T. Bendib, Proceedings of the 5th International Conference on Design and Technology of Integrated Systems in Nanoscale Era (Hammamet, Tunisia 2010 Mar. 23-25) p. 1. [http://dx.doi.org/10.1109/DTIS.2010.5487568].

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