Proceedings of the IEEK Conference (대한전자공학회:학술대회논문집)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Optimization of 70nm nMOSFET Performance using gate layout

게이트 레이아웃을 이용한 70nm nMOSFET 초고주파 성능 최적화

  • Hong, Seung-Ho (Department of Electronic and Electrical Engineering Pohang University of Science and Technology) ;
  • Park, Min-Sang (Department of Electronic and Electrical Engineering Pohang University of Science and Technology) ;
  • Jung, Sung-Woo (Department of Electronic and Electrical Engineering Pohang University of Science and Technology) ;
  • Kang, Hee-Sung (System LSI Division, Samsung Electronics Co., Ltd.) ;
  • Jeong, Yoon-Ha (Department of Electronic and Electrical Engineering Pohang University of Science and Technology)
  • 홍승호 (포항공과대학교 전자전기공학과) ;
  • 박민상 (포항공과대학교 전자전기공학과) ;
  • 정성우 (포항공과대학교 전자전기공학과) ;
  • 강희성 (삼성전자 System LSI 사업부) ;
  • 정윤하 (포항공과대학교 전자전기공학과)
  • Published : 2006.06.21
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Abstract

In this paper, we investigate three different types of multi-fingered layout nMOSFET devices with varying $W_f$(unit finger width) and $N_f$(number of finger). Using layout modification, we improve $f_T$(current gain cutoff frequency) value of 15GHz without scaling down, and moreover, we decrease $NF_{min}$(minimum noise figure) by 0.23dB at 5GHz. The RF noise can be reduced by increasing $f_T$, choosing proper finger width, and reducing the gate resistance. For the same total gate width using multi-fingered layout, the increase of finger width shows high $f_T$ due to the reduced parasitic capacitance. However, this does not result in low $NF_{min}$ since the gate resistance generating high thermal noise becomes larger under wider finger width. We can obtain good RF characteristics for MOSFETs by using a layout optimization technique.

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