• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.915-918
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• 2007

We have grown $SiO_2$ film on a polycrystalline Si layer using excited ozone gas, which is produced by ultra-violet light irradiation to ozone gas, without heating substrate. The obtained $SiO_2$ film shows dielectric properties comparable to the device quality films measured at the MIS capacitor configuration.

• Transactions on Electrical and Electronic Materials
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• v.3 no.3
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• pp.14-17
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• 2002

The HDP (High Density Plasma) CVD process consists of a simultaneous sputter etch and chemical vapor deposition. As CMOS process continues to scale down to sub- quarter micron technology, HDP process has been widely used fur the gap-fill of small geometry metal spacing in inter-metal dielectric process. However, HBP CVD system has some potential problems including plasma-induced damage. Plasma-induced gate oxide damage has been an increasingly important issue for integrated circuit process technology. In this paper, thin gate oxide charge damage caused by HDP deposition of inter-metal dielectric was studied. Multiple step HDP deposition process was demonstrated in this work to prevent plasma-induced damage by introducing an in-situ top SiH$_4$ unbiased liner deposition before conventional deposition.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.14 no.2
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• pp.47-49
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• 2004

Gate protection $SiN_x$ as an alternative to a conventional re-oxidation process in Dynamic Random Access Memory devices is investigated. This process can not only protect the gate electrode tungsten against oxidation, but also save the thermal budget due to the re-oxidation. The protection $SiN_x$ process is applied to the poly-Si gate, and its device performance is measured and compared with the re-oxidation processed poly-Si gate. The results on the gate dielectric integrity show that etch damage-curing capability of protection $SiN_x$ is comparable to the re-oxidation process. In addition, the hot carrier immunity of the $SiN_x$ deposited gate is superior to that of re-oxidation processed gate.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.104-104
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• 2009

Critical dimensions has rapidly shrunk to increase the degree of integration and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate insulator layer and the low conductivity characteristic of poly-silicon. To cover these faults, the study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$ and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-silicon gate is not compatible with high-k materials for gate-insulator. To integrate high-k gate dielectric materials in nano-scale devices, metal gate electrodes are expected to be used in the future. Currently, metal gate electrode materials like TiN, TaN, and WN are being widely studied for next-generation nano-scale devices. The TaN gate electrode for metal/high-k gate stack is compatible with high-k materials. According to this trend, the study about dry etching technology of the TaN film is needed. In this study, we investigated the etch mechanism of the TaN thin film in an inductively coupled plasma (ICP) system with $O_2/BCl_3/Ar$ gas chemistry. The etch rates and selectivities of TaN thin films were investigated in terms of the gas mixing ratio, the RF power, the DC-bias voltage, and the process pressure. The characteristics of the plasma were estimated using optical emission spectroscopy (OES). The surface reactions after etching were investigated using X-ray photoelectron spectroscopy (XPS) and auger electron spectroscopy (AES).

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.2
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• pp.117-123
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• 2004

A 30 nm $In_{0.7}GaAs$ High Electron Mobility Transistor (HEMT) with triple-gate has been successfully fabricated using the $SiO_2/SiN_x$ sidewall process and BCB planarization. The sidewall gate process was used to obtain finer lines, and the width of the initial line could be lessened to half by this process. To fill the Schottky metal effectively to a narrow gate line after applying the developed sidewall process, the sputtered tungsten (W) metal was utilized instead of conventional e-beam evaporated metal. To reduce the parasitic capacitance through dielectric layers and the gate metal resistance ($R_g$), the etchedback BCB with a low dielectric constant was used as the supporting layer of a wide gate head, which also offered extremely low Rg of 1.7 Ohm for a total gate width ($W_g$) of 2x100m. The fabricated 30nm $In_{0.7}GaAs$ HEMTs showed $V_{th}$of -0.4V, $G_{m,max}$ of 1.7S/mm, and $f_T$ of 421GHz. These results indicate that InGaAs nano-HEMT with excellent device performance could be successfully fabricated through a reproducible and damage-free sidewall process without the aid of state-of-the-art lithography equipment. We also believe that the developed process will be directly applicable to the fabrication of deep sub-50nm InGaAs HEMTs if the initial line length can be reduced to below 50nm order.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.156-161
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• 2017

This work presents a novel structure for junction-less tunneling field effect transistor (JL-TFET) with a floating gate over the source region. Introduction of floating gate instead of fixed metal gate removes the limitation of fabrication process suitability. The proposed device is based on a heavily n-type-doped Si-channel junction-less field effect transistor (JLFET). A floating gate over source region and a control-gate with optimized metal work-function over channel region is used to make device work like a tunnel field effect transistor (TFET). The proposed device has exhibited excellent ID-VGS characteristics, ION/IOFF ratio, a point subthreshold slope (SS), and average SS for optimized device parameters. Electron charge stored in floating gate, isolation oxide layer and body doping concentration are optimized. The proposed JL-TFET can be a promising candidate for switching performances.

• Proceedings of the Materials Research Society of Korea Conference
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• 2007.11a
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• pp.49.2-49.2
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• 2007

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.19-24
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• 2004

In this paper, we have demonstrated the fabrication of a 70 nm foot print of the T-gate by using a positive resist ZEP520/P(MMA-MAA)/PMMA trilayer by double exposure method without a thin dielectric supporting layer on the substrate. The device performance was characterized by DC and RF measurement. The fabricated 70 nm InGaAs/InAlAs MHEMTS with 70 ${\mu}{\textrm}{m}$ unit gate width and 2 fingers showed good DC and RF characteristics of Idss, max =228.6 mA/mm, gm =645 mS/mm, and fT =255 GHz, respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.19 no.12
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• pp.1140-1143
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• 2006

We report on the fabrication of P3HT-based thin-film transistors (TFTs) for liquid crystal display that consist of $NiO_x$, poly-vinyl phenol (PVP), and Ni for the source-drain (S/D) electrodes, gate dielectric layer, and gate electrode, respectively The $NiO_x$ S/D electrodes of which the work function is well matched to that of P3HT are deposited on a P3HT channel by electron-beam evaporation of NiO powder. The maximum saturation current of our P3HT-based TFT is about $15{\mu}A$ at a gate bias of -30 V showing a high field effect mobility of $0.079cm^2/Vs$ in the dark, and the on/off current ratio of our TFT is about $10^5$. It is concluded that jointly adopting $NiO_x$ for the S/D electrodes and PVP for gate dielectric realizes a high-quality P3HT-based TFT.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.1
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• pp.27-32
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• 2003

Highly reproducible side-wall process for the fabrication of the fine gate length as small as 40nm was developed. This process was utilized to fabricate 40nm InGaAs HEMTs with the 65% strained channel. With the usage of the dual $SiO_2$ and $SiN_x$ dielectric layers and the proper selection of the etching gas, the final gate length (Lg) was insensitive to the process conditions such as the dielectric over-etching time. From the microwave measurement up to 40GHz, extrapolated fT and fmax as high as 371 and 345 GHz were obtained, respectively. We believe that the developed side-wall process would be directly applicable to finer gate fabrication, if the initial line length is lessened below the l00nm range.