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40nm InGaAs HEMT's with 65％ Strained Channel Fabricated with Damage-Free $SiO_2/SiN_x$ Side-wall Gate Process  

Kim, Dae-Hyun (School of Electrical and Computer Engineering, Seoul National University)
Kim, Suk-Jin (School of Electrical and Computer Engineering, Seoul National University)
Kim, Young-Ho (School of Electrical and Computer Engineering, Seoul National University)
Kim, Sung-Wong (School of Electrical and Computer Engineering, Seoul National University)
Seo, Kwang-Seok (School of Electrical and Computer Engineering, Seoul National University)
Publication Information
JSTS:Journal of Semiconductor Technology and Science / v.3, no.1, 2003 , pp. 27-32 More about this Journal
Abstract
Highly reproducible side-wall process for the fabrication of the fine gate length as small as 40nm was developed. This process was utilized to fabricate 40nm InGaAs HEMTs with the 65% strained channel. With the usage of the dual $SiO_2$ and $SiN_x$ dielectric layers and the proper selection of the etching gas, the final gate length (Lg) was insensitive to the process conditions such as the dielectric over-etching time. From the microwave measurement up to 40GHz, extrapolated fT and fmax as high as 371 and 345 GHz were obtained, respectively. We believe that the developed side-wall process would be directly applicable to finer gate fabrication, if the initial line length is lessened below the l00nm range.
Keywords
InP; HEMT; InGaAs/InAlAs; nano-scale; side-wall; current-gain cutoff frequency (fT);
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