• Title/Summary/Keyword: device parameter

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An Analytical Expression for Current Gain of an IGBT

  • Moon, Jin-Woo;Chung, Sang-Koo
    • Journal of Electrical Engineering and Technology
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    • v.4 no.3
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    • pp.401-404
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    • 2009
  • A simple analytical expression for a current gain of IGBT is derived in terms of the device parameters as well as a gate length dependent parameter, which allows for the determination of the current components of the device as a function of its gate length. The analytical results are compared with those from simulation results. A good agreement is found.

Design of Energy Absorbing Braces (가새형 소성변형감쇠기의 설계 방법에 관한 연구)

  • 김진구;이강준
    • Proceedings of the Computational Structural Engineering Institute Conference
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    • 2000.10a
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    • pp.265-272
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    • 2000
  • Unbond brace hysteretic dampers are generally used to prevent or decrease structural damage in buildings subjected to strong earthquake by its energy dissipating hysteretic behavior. According to a previous research, the optimum ratio of device yield strength to story yield strength of the combined system has been identified as the most important parameter for characterizing the performance of this device. In this research, the validity and the applicability of the previous research has been investigated and a new approach has been proposed through earthquake response analysis of a steel structure installed with unbond brace type hysteretic damper.

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RF Modeling of Silicon Nanowire MOSFETs (실리콘 나노와이어 MOSFET의 고주파 모델링)

  • Kang, In-Man
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.47 no.9
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    • pp.24-29
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    • 2010
  • This paper presents the RF modeling for silicon nanowire MOSFET with 30 nm channel length and 5 nm channel radius. Equations for analytical parameter extraction are derived by analysis of Y-parameter. Accuracies of the new model and extracted parameters have been verified by 3-dimensional device simulation data up to 100 GHz. The model verifications are performed under conditions of saturation region ($V_{gs}$ = $_{ds}$ = 1 V) and linear region ($V_{gs}$ = 1 V, $V_{ds}$ = 0.5 V). The RMS modeling error of Y-parameters was calculated to be 1 %.

TLP Properties Evaluation of ESD Protection Device of GGNMOS Type for Conventional CMOS Process (Conventional CMOS 공정을 위한 GGNMOS Type의 ESD 보호소자의 TLP 특성 평가)

  • Lee, Tae-Il;Kim, Hong-Bae
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.21 no.10
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    • pp.875-880
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    • 2008
  • In this paper, we deal with the TLP evaluation results for GGNMOS in ESD protection device of conventional CMOS process. An evaluation parameter for GGNMOS is that repeatability evaluation for reference device($W/L=50\;{\mu}m1.0\;{\mu}m$) and following factors for design as gate width, number of finger, present or not for N+ gurad -ring, space of N-field region to contact and present or not for NLDD layer. The result of repeatability was showed uniformity of lower than 1 %. The result for design factor evaluation was ; 1) gate width leading to increase It2, 2) An increase o( finger number was raised current capability(It2), and 3) present of N+ gurad-ring was more effective than not them for current sink. Finally we suggest the optimized design conditions for GGNMOS in evaluated factor as ESD protection device of conventional CMOS process.

Analytical Model of Double Gate MOSFET for High Sensitivity Low Power Photosensor

  • Gautam, Rajni;Saxena, Manoj;Gupta, R.S.;Gupta, Mridula
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.13 no.5
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    • pp.500-510
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    • 2013
  • In this paper, a high-sensitivity low power photodetector using double gate (DG) MOSFET is proposed for the first time using change in subthreshold current under illumination as the sensitivity parameter. An analytical model for optically controlled double gate (DG) MOSFET under illumination is developed to demonstrate that it can be used as high sensitivity photodetector and simulation results are used to validate the analytical results. Sensitivity of the device is compared with conventional bulk MOSFET and results show that DG MOSFET has higher sensitivity over bulk MOSFET due to much lower dark current obtained in DG MOSFET because of its effective gate control. Impact of the silicon film thickness and gate stack engineering is also studied on sensitivity.

Analysis of Isolation System in Distinct Multi-mechanism HIF Device (이종 복합 메카니즘 HIF 기구의 충격저감시스템 해석)

  • Choe Eui Jung;Kim Hyo-Jun
    • Journal of the Korean Society for Precision Engineering
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    • v.22 no.2
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    • pp.53-59
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    • 2005
  • In this study, the isolation system for multi-mechanism HIF (high impulsive force) device has been investigated. For this purpose, parameter optimization process has been performed based on the simplified isolation system model under constraints of moving displacement and transmitted force. The design parameters for multi-mechanism HIF device have been derived with respect to HIF system I and HIF system II, respectively. In order to implement the dynamic absorbing system, the dual stage hydro-pneumatic damper and magnetorheological damper with semi-active control scheme are considered. Finally, the performance of the designed prototype isolation system has been evaluated by experimental works under actual operating conditions.

Small signal model and parameter extraction of SOI MOSFET's (SOI MOSFET's의 소신호 등가 모델과 변수 추출)

  • Lee, Byung-Jin;Park, Sung-Wook;Ohm, Woo-Yong
    • 전자공학회논문지 IE
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    • v.44 no.2
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    • pp.1-7
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    • 2007
  • The increasing high frequency capabilities of CMOS have resulted in increased RF and analog design in CMOS. Design of RF and analog circuits depends critically on device S-parameter characteristics, magnitude of real and imaginary components and their behavior as a function of frequency. Utilization of scaled high performance CMOS technologies poses challenges as concerns for reliability degradation mechanisms increase. It is important to understand and quantify the effects of the reliability degradation mechanisms on the S-parameters and in turn on small signal model parameters. Various physical effects influencing small-signal parameters, especially the transconductance and capacitances and their degradation dependence, are discussed in detail. The measured S-parameters of H-gate and T-gate devices in a frequency range from 0.5GHz to 40GHz. All intrinsic and extrinsic parameters are extracted from S-parameters measurements at a single bias point in saturation. In this paper we discuss the analysis of the small signal equivalent circuits of RF SOI MOSFET's verificated for the purpose of exacting the change of parameter of small signal equivalent model followed by device flame.

Resistance Switching Mechanism of Metal-Oxide Nano-Particles Memory on Graphene Layer

  • Lee, Dong-Uk;Kim, Dong-Wook;Kim, Eun-Kyu
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.08a
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    • pp.318-318
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    • 2012
  • A graphene layer is most important materials in resent year to enhance the electrical properties of semiconductor device due to high mobility, flexibility, strong mechanical resistance and transparency[1,2]. The resistance switching memory with the graphene layer have been reported for next generation nonvolatile memory device[3,4]. Also, the graphene layer is able to improve the electrical properties of memory device because of the high mobility and current density. In this study, the resistance switching memory device with metal-oxide nano-particles embedded in polyimide layer on the graphene mono-layer were fabricated. At first, the graphene layer was deposited $SiO_2$/Si substrate by using chemical vapor deposition. Then, a biphenyl-tetracarboxylic dianhydride-phenylene diamine poly-amic-acid was spin coated on the deposited metal layer on the graphene mono-layer. Then the samples were cured at $400^{\circ}C$ for 1 hour in $N_2$ atmosphere after drying at $135^{\circ}C$ for 30 min through rapid thermal annealing. The deposition of aluminum layer with thickness of 200 nm was done by a thermal evaporator. The electrical properties of device were measured at room temperature using an HP4156a precision semiconductor parameter analyzer and an Agilent 81101A pulse generator. We will discuss the switching mechanism of memory device with metal-oxide nano-particles on the graphene mono-layer.

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Optimal Design of ESD Protection Device with different Channel Blocking Ion Implantation in the NSCR_PPS Device (NSCR_PPS 소자에서 채널차단 이온주입 변화에 따른 최적의 정전기보호소자 설계)

  • Seo, Yong-Jin;Yang, Jun-Won
    • Journal of Satellite, Information and Communications
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    • v.11 no.4
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    • pp.21-26
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    • 2016
  • The ESD(electrostatic discharge) protection performance of PPS(PMOS pass structure) embedded N-type silicon controlled rectifier(NSCR_PPS) device with different implant of channel blocking region was discussed for high voltage I/O applications. A conventional NSCR standard device shows low on-resistance, low snapback holding voltage and low thermal breakdown voltage, which may cause latch-up problem during normal operation. However, our proposed NSCR_PPS devices with modified channel blocking structure demonstrate the improved ESD protection performance as a function of channel implant variation. Therefore, the channel blocking implant was a important parameter. Since the modified device with CPS_PDr+HNF structure satisfied the design window, we confirmed the applicable possibility as a ESD protection device for high voltage operating microchips.

Analysis of the spontaneous emission spectrum of a multisection DFB structure device (다중 구역 DFB 구조 소자의 자연 방출 스펙트럼에 관한 해석)

  • 정기숙;김부균;이봉영
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.33A no.7
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    • pp.230-244
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    • 1996
  • We derive analytic expressions for the spontaneous emission spectrum (SES) of a multisection distributed feedback (DFB) structure device employing complex coupled gratings including the effects of both facets reflections. The multisection DFB structure device used in the analysis is a general model which allows the independent phase of a grating in each section, and the sections without gratings. The expressions are the same as those derived by makino and glinski in case the gratings are index coupled and the phase of a grating in each section, ${\varphi}_k$ is '0' which means the phase of gratings in the device is ocntinuous. The expressions for the SES of a phase-shift-controlled (PSC) DFB structure device using tunable devices are derived from the general expressions. The number of parametes of the expressions is reduced by using the parameter of effective phase shift defined by the sum of the phase shift in a PSC region and the difference of the phase of a grating in each active region. Equations showing the effect of both facets reflections and the effective phase shift on the SES are derived. The validaty of the equations is verified by computer simultions. Computer simulation results also show the possibility of evaluating the structure parametes of the device from its SES.

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