• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.450-453
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• 1999

In this paper, The relationship between device performance and channel length(1.5-50$\mu$m) in polysilicon thin-film transistors fabricated by SPC technology was Investigated by measuring electric Properties such as 1-V characteristics, field effect mobility, threshold voltage, subthreshold swing, and trap density in grain boundary with channel length. The drain current at ON-state increases with decreasing channel length due to increase of the drain field, while OFF-state current (leakage current) is independent of channel length. The field effect mobility decrease with channel length due to decreasing carrier life time by the avalanche injection of the carrier at high drain field. The threshold voltage and subthreshold swing decrease with channel length, and then increase in 1.5 $\mu$m increase of increase of trap density in grain boundary by impact ionization.

• Proceedings of the Materials Research Society of Korea Conference
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• 1993.05a
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• pp.43-44
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• 1993

In this study SOI MOSFET model of the structure with 4-terminals and 3-interfaces is proposed. An SOI MOSFET is modeled with the equivalent circuit considered the interface capacitances. Parameters of SOI MOSFET device are extracted, and the electrical characteristics due to back-bias change is simulated. In SOI-MOSFET model device we describe the characteristics of threshold voltage, subthreshold slope, maxium electrical field and drain currents in the front channel when the back channel condition move into accmulation, depletion, and inversion regions respectively.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.1
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• pp.26-32
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• 2003

Then-channel poly-Si thin-film transistors (poly-Si TFT's) formed by solid phase crystallization (SPC) method on glass were measured to obtain the electrical parameters such as of I-V characteristics, mobility, leakage current, threshold voltage, and subthreshold slope. Then, devices were analyzed to obtain the reliability and appliability on TFT-LCD with large-size and high density. In n-channel poly-Si TFT with 5$\mu\textrm{m}$/2$\mu\textrm{m}$, 8$\mu\textrm{m}$, 30$\mu\textrm{m}$ devices of channel width/length, the field effect mobilities are 111, 116, 125 $\textrm{cm}^2$/V-s and leakage currents are 0.6, 0.1, and 0.02 pA/$\mu\textrm{m}$, respectively. Low threshold voltage and subthreshold slope, and good ON-OFF ratio are shown, as well. Thus. the poly-Si TFT's used by SPC are expected to be applied on TFT-LCD with large-size and high density, which can integrate the display panel and peripheral circuit on a targe glass substrate.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.3
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• pp.479-485
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• 2006

The double gate(DG) MOSFET is a promising candidate to further extend the CMOS scaling and provide better control of short channel effect(SCE). DGMOSFETs, having ultra thin undoped Si channel for SCEs control, ale being validated for sub-20nm scaling. A novel analytical transport model for the subthreshold mode of DGMOSFETs is proposed in this paper. The model enables analysis of short channel effect such as the subthreshold swing(SS), the threshold voltage roil-off$({\Delta}V_{th})$ and the drain induced barrier lowering(DIBL). The proposed model includes the effects of thermionic emission and quantum tunneling of carriers through the source-drain barrier. An approximative solution of the 2D Poisson equation is used for the distribution of electric potential, and Wentzel-Kramers-Brillouin approximation is used for the tunneling probability. The new model is used to investigate the subthreshold characteristics of a double gate MOSFET having the gate length in the nanometer range $(5-20{\sim}nm)$ with ultra thin gate oxide and channel thickness. The model is verified by comparing the subthreshold swing and the threshold voltage roll-off with 2D numerical simulations. The proposed model is used to design contours for gate length, channel thickness, and gate oxide thickness.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.718-722
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• 2006

The dependence of n-channel 2 shot SLS poly-Si TFT characteristics on the DOS (density of states) parameters was investigated by using a device simulation. Device performances were most sensitive to the DOS of poly-Si/gate insulator (GI) interface and poly-Si active layer. Deep level states at the poly-Si/GI interfaces strongly affect the subthreshold slope.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.291-293
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• 2000

In 64M DRAM, sub-1/4m NMOSFETs with STI(Shallow Trench Isolation), anomalous hump phenomenon of subthreshold region, due to capped p-TEOS/SiN interlayer induced defect, is reported. The hump effect was significantly observed as channel length is reduced, which is completely different from previous reports. Channel Boron dopant redistribution due to the defect should be considered to improve hump characteristics besides consideration of STI comer shape and recess.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.360-369
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• 2012

The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.

• Journal of Convergence for Information Technology
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• v.11 no.7
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• pp.104-110
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• 2021

A novel selective oxidation process has been developed for low source/drain (S/D) series resistance of the fin channel metal oxide semiconductor field effect transistor (MOSFET). Using this technique, the selective oxidation fin-channel MOSFET (SoxFET) has the gate-all-around structure and gradually enhanced S/D extension regions. The SoxFET demonstrated over 70% reduction in S/D series resistance compared to the control device. Moreover, it was found that the SoxFET behaved better in performance, not only a higher drive current but also higher transconductances with suppressing subthreshold swing and drain induced barrier lowering (DIBL) characteristics, than the control device. The saturation current, threshold voltage, peak linear transconductance, peak saturation transconductance, subthreshold swing, and DIBL for the fabricated SoxFET are 305 ㎂/㎛, 0.33 V, 13.5 𝜇S, 76.4 𝜇S, 78 mV/dec, and 62 mV/V, respectively.

• Journal of the Korean Vacuum Society
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• v.17 no.3
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• pp.199-203
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• 2008

The effects of surface treatment by $O_2$ plasma on the Bio-FETs were investigated by using the pseudo-MOSFETs on the SOI substrates. After a surface treatment by $O_2$ plasma with different RF powers, the current-voltage and field effect mobility of pseudo-MOSFETs were measured by applying back gate bias. The subthreshold characteristics of pseudo-MOSFETs were significantly degraded with increase of RF power. Additionally, a forming gas anneal process in 2 % diluted $H_2/N_2$ ambient was developed to recover the plasma process induced surface damages. A considerable improvement of the subthreshold characteristics was achieved by the forming gas anneal. Therefore, it is concluded that the pseudo-MOSFETs are a powerful tool for monitoring the surface treatment of Bio-FETs and the forming gas anneal process is effective for improving the electrical characteristics of Bio-FETs.

• Journal of Sensor Science and Technology
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• v.12 no.5
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• pp.218-224
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• 2003

The devices of n-channel poly silicon thin film transistors(TFTs) hydrogenated by plasma, $H_2$ and $H_2$/plasma processes are fabricated. The carriers sensitivity characteristics are analyzed with voltage bias stress at the gate oxide. The parametric sensitivity characteristics caused by electrical stress conditions in hydrogenated devices are investigated by measuring the drain current, threshold voltage($V_{th}$), subthreshold slope(S) and maximum transconductance($G_m$) values. As a analyzed results, the degradation characteristics in hydrogenated n-channel polysilicon thin film transistors are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si grain boundary due to dissolution of Si-H bonds. The generation of traps in gate oxide are mainly dued to hot electrons injection into the gate oxide from the channel region.