Browse > Article

Influence on Short Channel Effects by Tunneling for Nano structure Double Gate MOSFET  

Jung, Hak-Kee (군산대학교 전자정보공학부)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.10, no.3, 2006 , pp. 479-485 More about this Journal
Abstract
The double gate(DG) MOSFET is a promising candidate to further extend the CMOS scaling and provide better control of short channel effect(SCE). DGMOSFETs, having ultra thin undoped Si channel for SCEs control, ale being validated for sub-20nm scaling. A novel analytical transport model for the subthreshold mode of DGMOSFETs is proposed in this paper. The model enables analysis of short channel effect such as the subthreshold swing(SS), the threshold voltage roil-off$({\Delta}V_{th})$ and the drain induced barrier lowering(DIBL). The proposed model includes the effects of thermionic emission and quantum tunneling of carriers through the source-drain barrier. An approximative solution of the 2D Poisson equation is used for the distribution of electric potential, and Wentzel-Kramers-Brillouin approximation is used for the tunneling probability. The new model is used to investigate the subthreshold characteristics of a double gate MOSFET having the gate length in the nanometer range $(5-20{\sim}nm)$ with ultra thin gate oxide and channel thickness. The model is verified by comparing the subthreshold swing and the threshold voltage roll-off with 2D numerical simulations. The proposed model is used to design contours for gate length, channel thickness, and gate oxide thickness.
Keywords
나노구조;이중게이트 MOSFET;터널링;서브문턱스윙;문턱전압변화;드레인유기장벽저하;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 L.Chang, Y.K.Choi, D.Ha, P.Ranade, S,Xiong, J.Bokor, C.Hu and T.J.King, 'Extremely Scaled Silicon Nano-CMOS Devices,' Proc. of IEEE, vol.91, pp.1860-1873, 2003
2 J.R.Watling, A.R.Brown, and A.Asenov, 'Can the Density Gradient Approach Describe the Source-Drain Tunneling in Decanano Double-Gate MOSFETs?', Journal of Computational Electronics, vol.1, pp.289-293, 2002   DOI
3 D.Munteanu and J.L.Autran, 'Two-dimensional modeling of quantum ballistic transport in ultimate double-gate SOI devices', Solid-State Elec. vol.47, pp.1219-1225, 2003   DOI   ScienceOn
4 정학기, S. Dimitrijev, '더블게이트 MOSFET의 서브문턱스윙에 대한 연구', 한국해양정보통신학회논문지, vol.9, No.4, pp.804-810, 2005   과학기술학회마을
5 M.Bescond, J.L.Autran, D.Munteanu and M.Lannoo, 'Atomic-scale modeling of double gate MOSFETs using a tight- binding Green's function formalism', Solid-State Elec., vol.48, pp.567-574, 2004   DOI   ScienceOn
6 K.Kim and J.G.Foosum, 'Double-gate CMOS; Symmetrical versus asymmetrical gate devices,' IEEE Trans. Electron Devices, vol.48, pp.294-299, 2001   DOI   ScienceOn
7 T.Schulz, W.Rosner, E.Landgraf, L.Risch and U.Langmann, 'Planar and vertical double gate concepts,' Solid-State Electronics, vol.46, pp.985-989, 2002   DOI   ScienceOn
8 J.S.Park, H.Shin, D.Connelly, D. Yergeau, Z.Yu, and R.W.Dutton, 'Analysis of 2D quantum effects in the poly-gate and their impact on the short-channel effects in double-gate MOSFETs via the density-gradient method', Solid-State Electronics, vol.48, pp.1163-1168, 2004   DOI   ScienceOn
9 H.R.Huff and P.M.Zeitzoff, 'The Ultimate CMOS Device: A 2003 Perspective,' in the 2003 Int. Conf. Characterization and Metrology for ULSI Technology, pp.1-17, 2003