• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.39 no.5
• /
• pp.54-64
• /
• 2002

Recently System On a Chip(SoC) design based on IP cores has become the trend of If design To prevent the testing problem from becoming the bottleneck of the core-based design, defining of an efficient test architecture and a successful test methodology are mandatory. This paper describes a test architecture and a test control access mechanism for SoC based on IEEE 1149.1 boundary,scan. The proposed SoC test architecture is fully compatible with IEEE P1500 Standard for Embedded Core Test(SECT), and applicable for both TAPed cores and Wrapped cores within a SOC with the same test access mechanism. Controlled by TCK, TMS, TDI, and TDO, the proposed test architecture provides a hierarchical test feature.

• Journal of Broadcast Engineering
• /
• v.21 no.5
• /
• pp.792-802
• /
• 2016

Real time verification is necessary, since there are several features that cannot be verified through design simulation in the design of multiband soundbar system. And then this paper describes an implementation of an FPGA-based real-time verification system for a soundbar SoC with an embedded processor. It is verified a real-time performance test and a listening test which are several features in the design stage that cannot be verified through a design simulation. The measurement of quantitative specifications such as SNR, THD+N, frequency response, etc. as well as the listening test were performed through the implemented FPGA system, and it was verified that test results satisfied the target specifications.

• Journal of KIISE:Computer Systems and Theory
• /
• v.34 no.2
• /
• pp.84-92
• /
• 2007

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller and simplifies the test procedure and reduces the area overhead.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.1 s.343
• /
• pp.37-44
• /
• 2006

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller is simple in terms of test procedure and is small in terms of area overhead.

• The Journal of the Korea Contents Association
• /
• v.5 no.1
• /
• pp.229-236
• /
• 2005

Testing time and power consumption during testing System-On-a-Chip (SOC) are becoming increasingly important as the IP core increases in a SOC. We present a new algorithm to reduce the scan-in power and test data volume using the modified scan latch reordering. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.2
• /
• pp.61-68
• /
• 2008

This paper introduces an embedded core test wrapper for AMBA based System-on-Chip(SoC) test. The proposed test wrapper is compatible with IEEE 1500 and can be controlled by ARM Test Interface Controller(TIC). We use IEEE 1500 wrapper boundary registers as temporal registers to load test results as well as test patterns and apply a modified scan test procedure. Test time is reduced by simultaneously performing primary input insertion and primary output observation as well as scan-in and scan-out.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.52 no.10
• /
• pp.47-55
• /
• 2015

To verify the function of vehicle is becoming more and more difficult because many electronic control units have been embedded in vehicle with development of electronics industry. The reliability of vehicle should be considered above all important because malfunction of vehicle can cause damage of human life. In this paper, defect diagnosis platform based on CAN network is proposed to improve the reliability of vehicle. Reliability of vehicle is significantly increased by adopting the structural test via dedicated test path after manufacturing. Besides, the test cost is reduced because additional test pins are not required.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.5 s.335
• /
• pp.39-46
• /
• 2005

This paper introduces a new At-speed Interconnect Test Controller (ASITC) that can detect and diagnose dynamic as well as static defects in an SoC. SoC is comprised of IEEE 1149.1 and P1500 wrapped cores which can be operated by multiple system clocks. In other to test such a complicated SoC, we designed a interface module for P1500 wrapped cores and the ASITC that makes it possible to detect interconnect delay faults during 1 system clock from launching to capturing the transition signal. The ASITC proposed requires less area overhead than other approaches and the operation was verified through the FPGA implementation

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.41 no.11
• /
• pp.87-95
• /
• 2004

This paper proposes a new test data compression/decompression method for SoC(Systems-on-a-Chip). The method is based on analyzing the factors that influence test parameters: compression ratio and hardware overhead. To improve compression ratio, the proposed method is based on Modified Statistical Coding (MSC) and Input Reduction (IR) scheme, as well as a novel mapping and reordering algorithm proposed in a preprocessing step. Unlike previous approaches using the CSR architecture, the proposed method is to compress original test data and decompress the compressed test data without the CSR architecture. Therefore, the proposed method leads to better compression ratio with lower hardware overhead than previous works. An experimental comparison on ISCAS '89 benchmark circuits validates the proposed method.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.1
• /
• pp.14-19
• /
• 2008

Semiconductor testing area challenges many testing issues due to the minimization and ultra high performance of current semiconductors. Among these issues, signal integrity test on interconnections must be solved for highly integrated circuits like SoC. In this paper, we propose an effective pattern application method for signal integrity test on interconnects. Proposed method can be applied by using boundary scan architecture and very efficient test can be preceded with pretty short test time.