[KSCI] Korea Science Citation Index Service

At-speed Interconnect Test Controller for SoC with Multiple System Clocks and Heterogeneous Cores

Jang Yeonsil (Department of Computer Science & Engineering, Hanyang Univ.)
Lee Hyunbin (Department of Computer Science & Engineering, Hanyang Univ.)
Shin Hyunchul (Department of Electronical Engineering Computer Science, Hanyang Univ.)
Park Sungju (Department of Electronical Engineering Computer Science, Hanyang Univ.)

Publication Information

Journal of the Institute of Electronics Engineers of Korea SD / v.42, no.5, 2005 , pp. 39-46 More about this Journal

Abstract

This paper introduces a new At-speed Interconnect Test Controller (ASITC) that can detect and diagnose dynamic as well as static defects in an SoC. SoC is comprised of IEEE 1149.1 and P1500 wrapped cores which can be operated by multiple system clocks. In other to test such a complicated SoC, we designed a interface module for P1500 wrapped cores and the ASITC that makes it possible to detect interconnect delay faults during 1 system clock from launching to capturing the transition signal. The ASITC proposed requires less area overhead than other approaches and the operation was verified through the FPGA implementation

Keywords

ASITC; at-speed; EXTEST; IEEE 1149.1; P1500;

Citations & Related Records

Reference

1	Jongchul Shin, Hyunjin Kim and Sungho Kang, 'At-speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks,' Design Automation and Test in Europe Conference, 1999 DOI
2	ERIK JAN MARINISSEN et al., 'On IEEE P1500's Standard for Embedded Core Test,' JOURNAL OF ELECTRONIC TESTING, pp. 365-383, 2002 DOI ScienceOn
3	K. Lofstrom, 'EARLY CAPTURE FOR BOUNDAR SCAN TIMING MEASUREMENTS,' Proceedings of IEEE International Test Conference, pp.417-422, 1996 DOI
4	S Park and T Kim, 'A New IEEE 1149.1 BOUNDARY SCAN DESIGN FOR THE DETECTION OF DELAY DEFECTS,' Design Automation and Test in Europe Conference, pp.458-462, 2000 DOI
5	IEEE Standard 1149.1-2001, 'IEEE Standard Test Access Port and Boundary-Scan Architecture,' IEEE, June 2001
6	IEEE P1500 SECT Wep site. http://grouper.ieee.org/ groups/1500/

KSCI

At-speed Interconnect Test Controller for SoC with Multiple System Clocks and Heterogeneous Cores 다중 시스템 클럭과 이종 코아를 가진 시스템 온 칩을 위한 연결선 지연 고장 테스트 제어기

At-speed Interconnect Test Controller for SoC with Multiple System Clocks and Heterogeneous Cores