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An Efficient Test Access Mechanism for System On a Chip Testing  

Song, Dong-Seop (Dept.of Electric Electronics Engineering, Yonsei University)
Bae, Sang-Min (Dept.of Electric Electronics Engineering, Yonsei University)
Gang, Seong-Ho (Dept.of Electric Electronics Engineering, Yonsei University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.39, no.5, 2002 , pp. 54-64 More about this Journal
Abstract
Recently System On a Chip(SoC) design based on IP cores has become the trend of If design To prevent the testing problem from becoming the bottleneck of the core-based design, defining of an efficient test architecture and a successful test methodology are mandatory. This paper describes a test architecture and a test control access mechanism for SoC based on IEEE 1149.1 boundary,scan. The proposed SoC test architecture is fully compatible with IEEE P1500 Standard for Embedded Core Test(SECT), and applicable for both TAPed cores and Wrapped cores within a SOC with the same test access mechanism. Controlled by TCK, TMS, TDI, and TDO, the proposed test architecture provides a hierarchical test feature.
Keywords
IEEE 1149.1; IEEE P1500;
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