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Efficient AMBA Based System-on-a-chip Core Test With IEEE 1500 Wrapper  

Yi, Hyun-Bean (Department of Computer Science & Engineering, Hanyang University)
Han, Ju-Hee (Department of Computer Science & Engineering, Hanyang University)
Kim, Byeong-Jin (Department of Computer Science & Engineering, Hanyang University)
Park, Sung-Ju (Department of Computer Science & Engineering, Hanyang University)
Publication Information
Abstract
This paper introduces an embedded core test wrapper for AMBA based System-on-Chip(SoC) test. The proposed test wrapper is compatible with IEEE 1500 and can be controlled by ARM Test Interface Controller(TIC). We use IEEE 1500 wrapper boundary registers as temporal registers to load test results as well as test patterns and apply a modified scan test procedure. Test time is reduced by simultaneously performing primary input insertion and primary output observation as well as scan-in and scan-out.
Keywords
AMBA; IEEE 1500; System-on-Chip Test; Scan Test;
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Times Cited By KSCI : 1  (Citation Analysis)
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1 민필재, 송재훈, 이현빈, 박성주, "AMBA 기반 SoC 테스트를 위한 접근 메커니즘 설계," 대한전자공학회 논문지, Vol. 43, No. 10, Oct. 2006   과학기술학회마을
2 C. Lin and H. Liang, "Bus-Oriented DFT Design for Embedded Cores," IEEE Asia-Pacific Conference, Volume 1, pp. 561-563, Dec. 2004
3 ARM IHI 0011A, "AMBA Specification (Rev 2.0)". May 1999
4 E. J. Marnissen, S. K. Goel and M. Lousberg, "Wrapper Design for Embedded Core Test," IEEE International Test Conference, pp. 911-920, Oct. 2000
5 C. Feige et al, "Integration of the Scan-Test Method into an Architecture Specific Core-Test Approach," Journal of Electronic Testing, Volume 14, pp. 125-131, July 1998   DOI
6 Y. Zorian, E. J. Marinissen and S. Dey, "Testing Embedded-corebasedSystem Chips," Proceedings of IEEE International Test Conference, pp. 130-143, Oct. 1998
7 Christian Piguet, "Low-Power CMOS Circuits Technology Logic Design and CAD Tools," Taylor & Francis. 2005
8 Matthias Beck, Olivier Barondeau, Martin Kaibel, Frank Poehl, Lin Xijiang, Ron Press, "Logic Design For On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality," Proceedings of the Design, Automation and Test in Europe, 2005
9 M. Abramovici, M. Breuer, and A. Friedman, "Digital Systems Testing and Testable Design," IEEE Press, New York, 1990
10 IEEE Computer Society, "IEEE Standard Testability Method for Embedded Core-based Integrated Circuits," Aug. 2005
11 J. Gaisler and E. Catovic, "Gaisler Research IP Core's Manual," version 1.0.1, Jun. 2005