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An Efficient Test Data Compression/Decompression Using Input Reduction  

전성훈 (연세대학교 전기전자공학과)
임정빈 (연세대학교 전기전자공학과)
김근배 (연세대학교 전기전자공학과)
안진호 (연세대학교 전기전자공학과)
강성호 (연세대학교 전기전자공학과)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.41, no.11, 2004 , pp. 87-95 More about this Journal
Abstract
This paper proposes a new test data compression/decompression method for SoC(Systems-on-a-Chip). The method is based on analyzing the factors that influence test parameters: compression ratio and hardware overhead. To improve compression ratio, the proposed method is based on Modified Statistical Coding (MSC) and Input Reduction (IR) scheme, as well as a novel mapping and reordering algorithm proposed in a preprocessing step. Unlike previous approaches using the CSR architecture, the proposed method is to compress original test data and decompress the compressed test data without the CSR architecture. Therefore, the proposed method leads to better compression ratio with lower hardware overhead than previous works. An experimental comparison on ISCAS '89 benchmark circuits validates the proposed method.
Keywords
Test data compression; decompression; input reduction; statistical code; decompression architecture;
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