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Interconnect Delay Fault Test in Boards and SoCs with Multiple System Clocks  

Lee Hyunbean (Dept. of Computer Science & Engineering, Hanyang Univ.)
Kim Younghun (Dept. of Computer Science & Engineering, Hanyang Univ.)
Park Sungju (Dept. of Electronical Engineering Computer Science, Hanyang Univ.)
Park Changwon (Korea Electronics Technology Institutes(KETI) Intelligent IT System Research Center)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.43, no.1, 2006 , pp. 37-44 More about this Journal
Abstract
This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller is simple in terms of test procedure and is small in terms of area overhead.
Keywords
Interconnect Delay Fault; SoC; IEEE 1149.1; P1500; Multiple Clocks;
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