참고문헌
- Y. Zorian, S. Dey, and M. J. Rodgers, 'Test of Future System on Chips,' In Proceedings International Conference on Computer Aided Design, pp. 392 - 400, 2000 https://doi.org/10.1109/ICCAD.2000.896504
- The International Technology Roadmap for Semiconductors, 1999 Edition, ITRS
- I. Hamzaoglu and J. H. Patel, 'Test set compaction algorithms for combinational circuits,' In Proceedings International Conference on Computer Aided Design, pp. 283-289, 1998 https://doi.org/10.1145/288548.288615
- I. Pormeranz, L. Reddy, and S. Reddy, 'Compactest: A method to generate compact test set for combinational circuits,' IEEE Transactions on Computer Aided Design, Vol. 12, pp. 1040-1049, 1993 https://doi.org/10.1109/43.238040
- M. Ishida, D. S. Ha, and T. Yamaguchi, 'Compact: A hybrid method for compressing test data,' In Proceedings IEEE VLSI Test Symposium, pp. 62 - 69, 1998 https://doi.org/10.1109/VTEST.1998.670850
- A. Chandra and K Chakrabarty, 'Frequency-Directed Run-Length (FDR) Codes with Application to System on a Chip Test Data Compression,' In Proceedings IEEE VLSI Test Symposium, pp. 114 - 121, 2001 https://doi.org/10.1109/VTS.2001.923416
- A. Chandra and K Chakrabarty, 'System-on-a-Oiip Test Data Compression and Decompression Architectures Based on Golomb Codes,' IEEE Transactions on Computer Aided Design, Vol. 20, pp. 113 - 120, 2001 https://doi.org/10.1109/43.913754
- A. El-Maleh, S. al Zahir, and E. Khan, 'A Geometric Primitives Based Compression Scheme for Tesing System-on-Chip,' In Proceedings for IEEE VLSI Test Symposium, pp. 114 - 121, 2001 https://doi.org/10.1109/VTS.2001.923418
- V. Iyengar, K. Chakrabarty and B. Murray, 'Deterministic Built In Pattern Generation for Sequential Circuits,' Journal of Electronics Testing: Theory and Applications, Vol. 15, pp. 97 - 114, 1999 https://doi.org/10.1023/A:1008384201996
- A. Jas, J. Ghosh-Dastidar, and N. A. Touba, 'Scan Vector Compression/Decompression Using Statistical Coding,' In Proceedings IEEE VLSI Test Symposium, pp. 114 - 121, 1999 https://doi.org/10.1109/VTEST.1999.766654
- A. Jas and N. Touba, 'Test Vector Decompression Via Cyclical Scan Chains and Its Application to Testing Core Based Designs,' In Proceedings IEEE International Test Conference, pp. 458 - 464, 1998 https://doi.org/10.1109/TEST.1998.743186
- A. Jas and N. Touba, 'Using Embedded Processor for Efficient Deterministic Testing of System-on-Chip,' In Proceedings International Conference on Computer Design, pp. 418 - 423, 1999 https://doi.org/10.1109/ICCD.1999.808576
- P. Y. Gonciari, B. M AI-Hashimi, and N. Nicolici, 'Improving Compression Ratio, Area Overhead, and Test Application Time for System-on-a-Chip Test Data Compression/Decompression,' In Proceedings Design, Automation and Test in Europe Conference and Exhibition, pp. 604 - 611, 2002 https://doi.org/10.1109/DATE.2002.998363
- C. A. Chen and S. K Gupta, 'Efficient BIST TPG Design and Test Set Compaction via Input Reduction,' IEEE Transactions on Computer Aided Design of Integrated Circuit and Systems, Vol. 17, pp. 692 - 705, 1998 https://doi.org/10.1109/43.712101
- H. K. Lee and D. S. Ha, 'On the Generation of Test Patterns for COmbinational Circuits,' Tech. report no.12_93, Department of Electrical Engineering, Virginia Tech
- D. Heidel, S. Dhong, P. Hofstee, M. Immediato, K. Nowka, J. Silaberman, and K. Stawiasz, 'High-speed Serialiazing/Deserializing Design for Test Methods for Evaluating a 1 GHz Microprocessor,' In Proceedings IEEE VLSI Test Symposium, pp. 234 - 238, 1998 https://doi.org/10.1109/VTEST.1998.670873