• ETRI Journal
• /
• v.35 no.1
• /
• pp.158-161
• /
• 2013

This letter proposes a low-power current-steering digital-to-analog converter (DAC). The proposed DAC reduces the clock power by cutting the clock signal to the current-source cells in which the data will not be changed. The 10-bit DAC is implemented using a $0.13-{\mu}m$ CMOS process with $V_{DD}$=1.2 V. Its area is $0.21\;mm^2$. It consumes 4.46 mW at a 1-MHz signal frequency and 200-MHz sampling rate. The clock power is reduced to 30.9% and 36.2% of a conventional DAC at 1.25-MHz and 10-MHz signal frequencies, respectively. The measured spurious free dynamic ranges are 72.8 dB and 56.1 dB at 1-MHz and 50-MHz signal frequencies, respectively.

• Proceedings of the KIEE Conference
• /
• 2001.07b
• /
• pp.729-732
• /
• 2001

Digital signal processors(DSP) are widely used in modern power conversion devices, ac motor drives. However, generating pulse-width modulation(PWM) gating signals requires so high sampling rates that most computation resources of the DSP must be devoted to generating them. This paper presents an ASIC realization of 2 channel space-vector PWM(SVPWM). The developed DSP(ECLDSP) board can transmit gating signals to 2 converter/inverter and control them. ECLDSP board is used for control the various kinds of power-quality improvement systems.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.597-598
• /
• 2008

In this paper, a sample design of I/O port of micro-processor using ODC(Output Don't Care) computation that is one of methods for Clock Gating applicable at the register transfer level(RTL). The ODC computation Method is applied at the point that estimate the value considering Don't Care Conditions from output of datapath to registers using clock in logic system. This paper also shows the results of reduce consumption power due to controlling clock that was supplied at registers. In Experimental results, ODC computation Method reduce power reductions of around 37.5%

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.14 no.2
• /
• pp.453-461
• /
• 2010

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of embedded RISC core and a clock-gating algorithm using ODC (Observability Don't Care) operation to improve the power consumption of the core. The branch prediction algorithm has a structure using BTB(Branch Target Buffer) and 4-way set associative cache has lower miss rate than direct-mapped cache. Pseudo-LRU Policy, which is one of the Line Replacement Policies, is used for decreasing the number of bits that store LRU value. The clock gating algorithm reduces dynamic power consumption. As a result of estimation of performance and dynamic power, the performance of the OpenRISC core applied the proposed architecture is improved about 29% and dynamic power of the core using Chartered $0.18{\mu}m$ technology library is reduced by 16%.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.9 no.4
• /
• pp.240-248
• /
• 2009

Moore's law has driven silicon technology scale down aggressively, and it results in significant increase of leakage current on nano-meter scale CMOS. Especially, in mobile devices, leakage current has been one of designers' main concerns, and thus many studies have introduced low power methodologies. However, there are few studies to minimize implementation cost in the mixed use of the methodologies to the best of our knowledge. In this paper, we introduce industrial applications of low power design methodologies for the decrease of leakage current. We focus on the design cost reduction of power gating and reverse body bias when used together. Also, we present voltage scale as an alternative to reverse body bias. To sustain gate leakage current, we discuss the adoption of high-$\kappa$ metal gate, which cuts gate leakage current by a factor of 10 in 32 nm CMOS technology. A 45 nm mobile SoC is shown as the case study of the mixed use of low power methodologies.

• Journal of Sensor Science and Technology
• /
• v.20 no.4
• /
• pp.230-233
• /
• 2011

In this paper, highly-efficient optical gating in a junction device based on vanadium dioxide($VO_2$) thin film grown by a sol-gel method was investigated as a gate terminal of a three-terminal device using infrared light with a wavelength of ~1554.6 nm. Due to the photoinduced phase transition, the threshold voltage of the $VO_2$ junction device, at which the device current abruptly jumps, could be tuned with a sensitivity of ~96.5 V/W by adjusting the optical power of the infrared light directly illuminating the device. Compared with the tuning efficiency of the previous device fabricated using $VO_2$ thin film deposited by a pulsed laser deposition method, the threshold voltage of this device could be tuned by ~76.8 % at an illumination power of ~39.8 mW resulting in a tuning efficiency of ~1.930 %/mW, which is ~4.9 times larger than the previous device.

• Proceedings of the KIEE Conference
• /
• 1995.07a
• /
• pp.431-433
• /
• 1995

Active Power Filters(APF) have been developed for several years to solve the harmonics disturbance problems on power system networks. This paper studies observer based digital algorithm and PWM technique for three phase current source APF by simulation. Both switching or outside white noises affect seriously at control signal for APF control system. Hence observer algorithm to reduce noises is used. A technique of generation gating patterns for the CSI topologies based on carrier PWM techniques is applied. The requirements imposed on gating signals are satisified by the appropriate combination of single phase switching patterns and short pulse generator.

• Journal of Electrical Engineering and Technology
• /
• v.7 no.5
• /
• pp.784-788
• /
• 2012

In this paper, a high-performance optical gating in a junction device based on a vanadium dioxide dioxide ($VO_2$) thin film grown by a sol-gel method was experimentally demonstrated by directly illuminating the $VO_2$ film of the device with an infrared light at ~1554.6 nm. The threshold voltage of the fabricated device could be tuned by ~76.8 % at an illumination power of ~39.8 mW resulting in a tuning efficiency of ~1.930 %/mW, which was ~4.9 times as large as that obtained in the previous device fabricated using the $VO_2$ thin film deposited by a pulsed laser deposition method. The rising and falling times of the optical gating operation were measured as ~50 ms and ~200 ms, respectively, which were ~20 times as rapid as those obtained in the previous device.

• Journal of Korea Society of Industrial Information Systems
• /
• v.18 no.6
• /
• pp.25-30
• /
• 2013

In nanoscale MOSFET technology, aging effects such as Negative Bias Temperature Instability(NBTI), Hot carrier Injection(HCI), Time Dependent Dielectric Breakdown (TDDB) and so on which affect circuit reliability can lead to severe degradation of digital circuit performance. Therefore, this paper has proposed the adaptive compensation circuit to overcome the aging effects of digital circuits. The proposed circuit deploys a power gating structure with variable power switch width and variable forward body-biasing voltage in order to adaptively compensate for aging induced performance degradation, and has been designed in 45nm technology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2008.10a
• /
• pp.289-292
• /
• 2008

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of OpenRISC processor and a clock gating algorithm using ODC (Observability Don't Care) operation for a low-power processor. The branch prediction algorithm has a structure using BTB(Branch Target Buffer) and 4-way set associative cache has lower miss rate than direct-mapped cache. The clock gating algorithm reduces dynamic power consumption. As a result of estimation of performance and dynamic power, the performance of the OpenRISC processor using the proposed algorithm is improved about 8.9% and dynamic power of the processor using samsung $0.18{\mu}m$ technology library is reduced by 13.9%.