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Design of a new adaptive circuit to compensate for aging effects of nanometer digital circuits  

Kim, Kyung Ki (대구대학교 전자전기공학부)
Publication Information
Journal of the Korea Industrial Information Systems Research / v.18, no.6, 2013 , pp. 25-30 More about this Journal
In nanoscale MOSFET technology, aging effects such as Negative Bias Temperature Instability(NBTI), Hot carrier Injection(HCI), Time Dependent Dielectric Breakdown (TDDB) and so on which affect circuit reliability can lead to severe degradation of digital circuit performance. Therefore, this paper has proposed the adaptive compensation circuit to overcome the aging effects of digital circuits. The proposed circuit deploys a power gating structure with variable power switch width and variable forward body-biasing voltage in order to adaptively compensate for aging induced performance degradation, and has been designed in 45nm technology.
Reliability; Aging effects; NBTI; PBTI; HCI; TDDB; Power gating; Forward body biasing voltage;
Citations & Related Records
Times Cited By KSCI : 3  (Citation Analysis)
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1 J. Keane , D. Persaud and C. H. Kim "An all-in-one silicon odometer for separately monitoring HCI, BTI, and TDDB", Proc. IEEE VLSI Circuits Conf., pp.108 -109 2009.
2 Yeon-Bo Kim, Kyung Ki Kim, "The Impact of TDDB Failure on Nanoscale CMOS Digital Circuits", Journal of the Korea Industrial Information System Society, V. 17, No. 3, pp.27-34, July 2012.   과학기술학회마을   DOI   ScienceOn
3 Kyung Ki Kim, "Analysis of Electromigration in Nanoscale CMOS Circuits," Journal of the Korea Industrial Information System Society, V. 18, No. 1, pp.19-24, Feb. 2013.   과학기술학회마을   DOI   ScienceOn
4 Kyung Ki Kim, "Minimal Leakage Pattern Generator," Journal of the Korea Industrial Information System Society, V. 16, No. 5, pp.1-8, Dec. 2011.   과학기술학회마을
5 Kyung Ki Kim, "On-chip Aging Sensor Circuits for Reliable Nanometer MOSFET Digital Circuits" Circuits and Systems II: Express Briefs, IEEE Transactions on, vol.57, no.1, pp.798-902, Oct.2010.
6 Kyung Ki Kim, " Adaptive HCI-aware power gating structure" Quality Electronic Design (ISQED), 2010 11th International Symposium on, pp. 219-224, March.2010.
7 Kyung Ki Kim, "Ultra-Voltage Power Gating Structure Using Low Threshold Voltage" Circuits and Systems (ISCAS), Proceedings of 2010 IEEE International Symposium on, vol.56, no.1, pp.926-930, Dec.2009.
8 S. Kim, S. Kosonocky, D. Knebel, "Understanding and minimizing ground bounce during mode transition of power gating structures", IEEE ISLPED, pp. 22-25, Aug. 2003.
9 P. Royannez, et. al., "90nm low leakage SoC design techniques for wireless applications", IEEE International Solid-State Circuits Conference, pp. 138-139, Feb. 2005.