• Proceedings of the KIPE Conference
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• 2013.11a
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• pp.56-57
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• 2013

불평형 및 왜곡 상태에서 정상분 추출은 기존 여러 가지 방법이 제시되어 있다. 여기에 PLL(Phase Locked Loop) 방식에 따라 다양한 특성이 나타나게 된다. 본 논문에서는 4가지 정상분 추출 방법과 2가지 PLL 방법을 적용하여 각각의 성능을 시뮬레이션 및 실험을 통해 비교 분석하였다.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.25 no.9
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• pp.903-911
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• 2014

This paper proposes a high speed frequency synthesizer with dual phase-locked loop(PLL) structure to improve phase noise level and shape in a wideband receiver. To reduce phase noise and fractional spur, a output frequency of $1^{st}$ PLL used as reference frequency of $2^{nd}$ PLL is changed. The frequency synthesizer has been designed with 1 Hz frequency resolution using digital NCO in 6.5~8.5 GHz wide spectrum. The measured results of the fabricated frequency synthesizer show that the output power is about -3 dBm, the maximum lock-in time and phase noise are within 60 us and -95 dBc/Hz at 10 kHz offset, respectively.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.1
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• pp.37-42
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• 2021

This paper presents a jitter and phase noise characteristic improved phase-locked loop (PLL) with loop filter voltage detector(LFVD) and frequency voltage converter(FVC). Loop filter output voltage variation is determined through a circuit made of resistor and capacitor. The output signal of a small RC time constant circuit is almost the same as to loop filter output voltage. The output signal of a large RC time constant circuit is the average value of loop filter output voltage and becomes a reference voltage to the added LFVD. The LFVD output controls the current magnitude of sub-charge pump. When the loop filter output voltage increases, LFVD decreases the loop filter output voltage. When the loop filter output voltage decreases, LFVD increases the loop filter output voltage. In addition, FVC also improves the phase noise characteristic by reducing the loop filter output voltage variation. The proposed PLL with LFVD and FVC is designed in a 0.18um CMOS process with 1.8V power voltage. Simulation results show 0.854ps jitter and 30㎲ locking time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.10
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• pp.2380-2386
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• 2013

A PLL with an unipolar charge pump and a loop filter consisting of sample-hold capacitor and 2nd-order RC filter has been proposed. The goal of the proposed PLL is the suppression of reference spur which is caused by charge pump mismatch. It also improves phase noise characteristic. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.7
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• pp.82-88
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• 2014

An available capacitance increasing phase-locked loop(PLL) with two voltage controlled oscillator gains has been proposed. In this paper, the available capacitance of loop filter is increased by using two positive/negative gains of voltage controlled oscillator (VCO). It results in 1/10 reduction in the size of loop filter capacitor. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and a locking time of conventional PLL.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2017.05a
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• pp.197-199
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• 2017

This paper presents a jitter characteristic improved phase locked loop (PLL) with an RC time constant circuit. In the RC time constant circuit, LPF's voltage is inputted to a comparator through small and large RC time constant circuits. The negative feedback loop reduces the variation of loop filter output voltage resulting in jitter characteristic improvement.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.2
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• pp.152-159
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• 2015

In a weak grid condition, the precise grid impedance estimation is essential to guaranteeing the high performance current control and power transfer for a grid-connected inverter. This study proposes a precise estimation method for grid impedance by PQ variations by employing the variation method of reference currents. The operation principle of grid impedance estimation is fully presented, and the negative impact of the phase locked loop is analyzed. Estimation error by a synchronization angle in the park's transformation using the phase locked loop is derived. As a result, the variation method of reference currents for accurate estimation is introduced. The validation of the proposed method is verified through several simulation results and experiments based on a 2-kW voltage source inverter prototype.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.955-958
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• 1999

We designed a phase locked loop (PLL), which is applicable to microprocessor clock generation application. The designed PLL has a new simple phase frequency detector (PFD) which eliminate dead-zone and has a good high frequency characteristic. The lock-in range of the designed PLL is 50 MHz ~ 150 MHz at 3.3v power supply voltage. The design is carried out using a 0.6${\mu}{\textrm}{m}$ triple metal CMOS process. The area of the layout is 0.35mm by 0.42mm with 359 transistors.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.5
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• pp.99-105
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• 2014

A reference spur suppressed PLL with two-symmetrical loops without changing the bandwidth which is optimized to suppress phase noise and reduce locking time has been designed. The principle of suppressing a reference signal spur is to stabilize the input voltage of voltage controlled oscillator (VCO). The proposed PLL consists of a phase-frequency detector(PFD) which has two outputs, two charge pumps(CP), two loop filters(LF), a divider and a VCO which has two inputs. Simulation results with $0.18{\mu}m$ CMOS process show that the reference spur is approximately suppressed to 1/2 of the reference spur in a conventional PLL. Even though there is a 5% process variation in the magnitude of R and C, the simulation result shows that the reference spur is still suppressed to 1/2 of the reference spur in a conventional PLL. The power consumption is 6.3mW at the power supply of 1.8V.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.13 no.4
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• pp.285-301
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• 1988

The symbol error rate equations of multi-level quadrature PRS(QPRS) system have been derived in the individual and composite environment of Gaussian/impulsive noise, cochannel CW interference, carrier offset, phase jitter and fading. And using the derived error rate equations, the probability of error has been evaluated and shown in graphs as functions of carrier to noise power ratio, carrier to interference power ratio, phase error, impulsive index, the ration of Gaussian noise to impulsive noise power component, signal to noise power ration in phase locked loop(PLL), and fading figures. The rseults show that the error rate performances are generally more more degraded by impulsive noise than by Gaussian noise. But on the contrary the erors occurred more frequently by Gaussian noise than impulsive noise in a fading environment.