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http://dx.doi.org/10.5573/ieie.2014.51.7.082

An Available Capacitance Increasing PLL with Two Voltage Controlled Oscillator Gains  

Jang, Hee-Seung (Dept of Electronics, Pukyong National University)
Choi, Young-Shig (Dept of Electronics, Pukyong National University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.51, no.7, 2014 , pp. 82-88 More about this Journal
Abstract
An available capacitance increasing phase-locked loop(PLL) with two voltage controlled oscillator gains has been proposed. In this paper, the available capacitance of loop filter is increased by using two positive/negative gains of voltage controlled oscillator (VCO). It results in 1/10 reduction in the size of loop filter capacitor. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and a locking time of conventional PLL.
Keywords
PLL; available capacitance increasing scheme; VCO;
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Times Cited By KSCI : 1  (Citation Analysis)
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1 Y. Koo, H. Huh, Y. Cho, J. Lee, J. Park, D. Jeong, and W. Kim, "A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS-and cellualr-CDMA wireless systems," IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 536-542, May 2002.   DOI   ScienceOn
2 B. Catli, A. Nazemi, T. Ali, S. Fallahi, Y. Liu, J. Kim, M. Abdul-Latif, M. R. Ahmadi, H. Maarefi, A. Momtaz, and N. Kocaman, "A 2sub-200 fs RMS jitter capacotor multiplier loop filter-based PLL in 28 nm CMOS for high-speed serial communication applications," in CICC, 2013, pp. 1-4.
3 J. Kim, J. Kim, B. Lee, N. Kim, D. Jeong, and W. Kim, "A 20-GHz phase-locked loop for 40-Gb/s serializing transmitter in 0.13-${\mu}m$ CMOS," IEEE J. Solid-State Circuits, vol. 41, no. 4, pp. 899-908, Apr. 2006.   DOI   ScienceOn
4 Youn-Gui Song, Young-Shig Choi and Ji-Goo Ryu, "A phase locked loop with resistance and capacitance scaling scheme," IEEK SD, vol. 46, no. 4, pp. 37-44, April 2009.   과학기술학회마을
5 L. Liu, T. Sakurai, and M. Takamiya, "A charge-domain auto- and cross-corrrelation based data synchronization schme with power-and area-efficient PLL for impulse radio UWB receiver," IEEE J. Solid-State Circuits, vol. 46, no. 6, pp. 1349-1359, June. 2011.   DOI   ScienceOn
6 I.-C. Hwang, "Area efficient and self-biased capacitor multiplier for on-chip loop filter," Electronics Lett. vol. 42, no. 24, pp. 1392-1393, Nov. 2006.   DOI   ScienceOn
7 J. Choi, J. Park W. Kim K. Lim, and J. Laskar, "Hihg multiplication factor capacitor multiplier for an on-chip PLL loop filter," Electronics Lett. vol. 45, no. 5, pp. 239-240, Feb. 2009.   DOI   ScienceOn
8 K. Shu, E. Sanchez-Sinencio, J. Silva-Martinez, and S. H. K. Embabi, "A 2.4-GHz monolithic fractional-N frequency synthesizer with robust phase-switching prescaler and loop capacotance multiplier," IEEE J. Solid-State Circuits, vol. 358, no. 6, pp. 866-874, June 2003.
9 S-R. Han, C-N. Chuang, and S-I. Liu, "A time-constant calibrated phase-locked loop with a fast-locked time," IEEE Trans. Circuits and Systems-II, vol. 54, no. 1, pp. 34-38, Jan. 2007.   DOI   ScienceOn
10 P. K. Hanumolu, M. Brownlee, K. Mayaram and U.-K. Moon, "Analysis of Charge-Pump Phase-Locked Loops," IEEE transactions on circuits and systems Fundamental theory and applications, Vol. 51, no. 9, pp. 1665-1674, Sep 2004.   DOI   ScienceOn
11 J. Craninckx and M. Steyaert, "A fully integrated CMOS DCS-1800 frequency synthesizer," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2054-2065, Dec. 1998.   DOI   ScienceOn
12 Y. Song and Z. Ignjatovic, "A high-performance OLL with a low-power active switchedcapacitor loop filter," IEEE Trans. Circuits and Systems-II, vol. 58, no. 9, pp. 555-559, Sept. 2011.   DOI   ScienceOn