A 50 to 150 MHz PLL with a New Phase Frequency Detector suitable for Microprocessor Application

마이크로프로세서 응용에 적합한 새로운 구조의 위상/주파수 검출기를 가지는50 to 150 MHz PLL

We designed a phase locked loop (PLL), which is applicable to microprocessor clock generation application. The designed PLL has a new simple phase frequency detector (PFD) which eliminate dead-zone and has a good high frequency characteristic. The lock-in range of the designed PLL is 50 MHz ~ 150 MHz at 3.3v power supply voltage. The design is carried out using a 0.6${\mu}{\textrm}{m}$ triple metal CMOS process. The area of the layout is 0.35mm by 0.42mm with 359 transistors.