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http://dx.doi.org/10.5573/ieie.2014.51.5.099

A Reference Spur Suppressed PLL with Two-Symmetrical Loops  

Choi, Hyun-Woo (Pukyong National University)
Choi, Young-Shig (Pukyong National University)
Publication Information
Journal of the Institute of Electronics and Information Engineers / v.51, no.5, 2014 , pp. 99-105 More about this Journal
Abstract
A reference spur suppressed PLL with two-symmetrical loops without changing the bandwidth which is optimized to suppress phase noise and reduce locking time has been designed. The principle of suppressing a reference signal spur is to stabilize the input voltage of voltage controlled oscillator (VCO). The proposed PLL consists of a phase-frequency detector(PFD) which has two outputs, two charge pumps(CP), two loop filters(LF), a divider and a VCO which has two inputs. Simulation results with $0.18{\mu}m$ CMOS process show that the reference spur is approximately suppressed to 1/2 of the reference spur in a conventional PLL. Even though there is a 5% process variation in the magnitude of R and C, the simulation result shows that the reference spur is still suppressed to 1/2 of the reference spur in a conventional PLL. The power consumption is 6.3mW at the power supply of 1.8V.
Keywords
Phase Locked Loop; Reference spur; Loop filter;
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