• Journal of electromagnetic engineering and science
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• 제11권1호
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• pp.62-69
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• 2011

This paper proposes a novel electrical characterization approach for a high-performance package system using an improved Partial Element Equivalent Circuit (PEEC). As the effect of interconnects becomes a pivotal factor for the performance of high-speed electronic systems, there is a great demand for an accurate equivalent model for interconnects. In particular, an equivalent model of interconnects is established in this paper for the Fine-Pitch Ball Grid Array (FBGA) package using the improved PEEC method. Based on the equivalent model, electrical characteristics are analyzed; furthermore, these are verified through the measurement results of a Vector Network Analyzer (VNA).

• 한국전기전자재료학회논문지
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• 제16권5호
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• pp.404-408
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• 2003

The characterization for several multi-layer embedded inductors with different structures was investigated. The optimized equivalent circuit models for several test structures were obtained from HSPICE. Building blocks are modeled using Partial element equivalent circuit method. The mean and the standard deviation of model parameters were extracted and predictive modeling was performed on different test structure. From this study, the characteristic of multi-layer inductors can be predicted.

• ETRI Journal
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• 제28권2호
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• pp.182-190
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• 2006

The circuit modeling of interdigitated capacitors fabricated by high-k low-temperature co-fired ceramic (LTCC) sheets was investigated. The s-parameters of each test structure were measured from 50 MHz to 10 GHz, and the modeling was performed using these measured sparameters up to the first resonant frequency. Each test structure was divided into appropriate building blocks. The equivalent circuit of each building block was composed based on the partial element equivalent circuit (PEEC) method. Modeling was executed to optimize the parameters in the equivalent circuit of each building block. The validity of the extracted parameters was verified by the predictive modeling for the test structures with different geometry. After that, Monte Carlo analysis and sensitivity analysis were performed based on the extracted parameters. The modeling methodology can allow a device designer to improve the yield and to save time and cost for the design and manufacturing of devices.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 하계학술대회 논문집 Vol.5 No.1
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• pp.130-133
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• 2004

The characterization of interdigitated capacitors was investigated. The test structures are manufactured by low temperature co-fired ceramic(LTCC) process and their s-parameters were measured. The optimized equivalent circuit models for test structures were obtained using the partial element equivalent circuit(PEEC) method. Predictive modeling was performed on different test structures using optimized parameters to verify the circuit models. From this result, the manufacturability on the process can be improved through the predictive modeling for the characteristics of interdigitated capacitors.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2005년도 하계학술대회 논문집 Vol.6
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• pp.57-58
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• 2005

The properties such as capacitance and resonant frequency are important in embedded capacitors. Accurate equivalent model is required to find these properties of embedded capacitor. In this paper, we investigate to analyze the properties of high-K embedded capacitor which was fabricated by Low Temperature Co-fired Ceramic (LTCC). Modeling based on partial element equivalent circuit (PEEC) method is performed using HSPICE circuit simulation. This modeling methodology can provide the good inspection of embedded capacitor to device engineer.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.2
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• pp.669-672
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• 2003

With the advances on wireless internet technology, many research on minimization of wireless LAN is on the progress. To apply passive components in MCM, characteristic analysis of passive components is essential. In this paper, three square spiral inductors were modeled by HSPICE using PEEC (Partial Element Equivalent Circuit) method. Afterwards, Monte-Carlo analysis was performed to evaluate the optimized parameters. This work will give an idea on PEEC modeling of spiral inductor, and enable researchers with predictive data before large scale manufacturing.

• 대한전자공학회논문지SD
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• 제43권12호
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• pp.23-32
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• 2006

다층 고속 디지털 보드에 대한 빠르고 정확한 전압 버스 설계 방법은 정확하고 정밀한 고속 보드에 전원 공급망 설계 방법을 위해 고안되었다. FAPUD는 PBEC(Path Based Equivalent Circuit)모델과 망 합성 방법의 두 중요 알고리즘을 기반으로 구성된다. PBEC 모델 기반의 회로 레벨의 2차원 전원 분배 망의 전기적 값으로부터 lumped 1차원 회로 모델로 간단한 산술 표현들을 활용한다 제안된 PBEC 기반인 회로 단계 설계는 제안한 지역 접근법을 이용해 수행된다. 이 회로 단계 설계는 온칩 디커플링 커패시터의 크기, 오프칩 디커플링 커패시터의 위치와 크기, 패키지 전압 버스의 유효한 인덕턴스를 직접 결정하고 계산한다. 설계 출력에 따라 모든 디커플링 커패시터가 포한된 lumped 회로 모델과 전압 버스의 레이아웃은 FAPUD 방법을 이용한 후 얻을 수 있다. 미세조정 과정에서, I/O Switching에 의해 덧붙여진 Simultaneous Switching Noise(SSN)를 고려한 보드 재 최적화가 수행될 수 있다 이는 전원 공급 잡음에 I/O 동작 효과가 lumped 회로 모델을 가지고 전 동작 주파수 범위에 대해 추산될 수 있기 때문이다. 게다가 만약 설계에 조정이 필요하거나 교체해야 한다면, FAPUD 방법은 다른 전면 설계변경 없이 디커플링 커패시터들을 대체하여 설계를 수정하는 것이 가능하다. 마지막으로 FAPUD 방법은 전형적인 PEEC 기본설계 방법과 비교해 정확하고 FAPUD 방법의 설계 시간은 전형적인 PEEC 기본 설계 방법의 시간보다 10배가 빠르다.

• ETRI Journal
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• 제28권3호
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• pp.347-354
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• 2006

The characteristic variation of 3-dimensional (3-D) solenoid-type embedded inductors is investigated. Four different structures of a 3-D inductor are fabricated by using a low-temperature co-fired ceramic (LTCC) process, and their s-parameters are measured between 50 MHz and 5 GHz. The circuit model parameters of each building block are optimized and extracted using the partial element equivalent circuit method and an HSPICE circuit simulator. Based on the model parameters, the characteristics of the test structures such as self-resonant frequency, inductance, and quality (Q) factor are analyzed, and predictive modeling is applied to the structures composed of a combination of the modeled building blocks. In addition, characteristic variations of the 3-D inductors with different structures using extracted building blocks are also investigated. This approach can provide a characteristic estimation of 3-D solenoid embedded inductors for structural variations.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.38-39
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• 2006

In this paper, we describe a method of accurate modeling capacitor in Low Temperature Co-fired Ceramic(LTCC). We obtain building blocks that present characterization of test structure through partial element equivalent circuit (PEEC) method. The extracted model of building blocks can be used for predicting behaviors of capacitors with different geometries. This method can provide the good inspection of capacitor to device engineer.

• 마이크로전자및패키징학회지
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• 제13권4호
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• pp.9-15
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• 2006

이 논문은 코어와 I/O 회로가 포함된 PEEC(Partial Equivalent Electrical Circuit) PDN(Power Distribution Networks)의 임피던스 변화에 따른 칩의 성능 분석을 나타내었다. I/O 전원에 연결된 코어 전원 잡음이 I/O 스위칭에 어떠한 영향이 미치는지 시뮬레이션 결과를 통하여 보였다. 또한 직접 설계한 $7{\times}5$인치 DLL(Delay Locked Loop)시험 보드를 사용하여 칩의 동작 지점에 따른 전원 잡음의 효과를 분석하였다. $50{\sim}400MHz$에 주파수 대역에 따른 DLL의 지터를 측정하고 시뮬레이션 결과로 얻어진 임피던스 값과 비교하였다. PDN의 공진 피크가 100MHz 주파수에서 1옴보다 큰 임피던스를 갖기 때문에 DLL의 지터는 주파수가 100MHz 근처에서 증가함을 보여준다. 타겟 임피던스를 줄이기 위한 방법인 디커플링 커패시터에 따른 칩과 보드의 임피던스 변화를 보였다. 따라서 전원 공급망 설계는 디커플링 커패시터와 함께 코어 스위칭 전류와 I/O 스위칭 전류를 같이 고려해야 한다.