• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.393-394
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• 2008

This paper presents a new method to extract the substrate resistance by fitting current-dependent base resistance of parasitic BJT without a complex RF extraction method. The extracted substrate resistance values using the new method match well with those using the RF one, verifying the accuracy of the proposed DC technique.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.12
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• pp.21-26
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• 2004

In this paper, a direct method is developed to extact RF equivalent circuit of a packaged BJT without optimization. First, parasitic components of plastic package are removed from measured S-parameters using open and short package patterns. Using package do-embedded S-parameters, a direct and simple method is proposed to extract bonding wire inductance and chip pad capacitance between package lead and chip pad. The small-signal model parameters of internal BJT are next determined by Z and Y-parameter formula derived from RF equivalent circuit. The modeled S-parameters of packaged BJT agree well with measured ones, verifying the accuracy of this new extraction method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.5
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• pp.16-21
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• 2012

For CMOS based bipolar junction transistor (BJT), a novel BJT structure which has higher matching property than conventional BJT structure was proposed and analyzed. The proposed structure shows a slight decrease of collector current density, $J_C$ about 0.361% and an increase of current gain, ${\beta}$ about 0.166% compared with the conventional structure. However, the proposed structure shows a decrease of area about 10% the improvement of matching characteristics of collector current ($A_{IC}$) and current gain ($A_{\beta}$) about 45.74% and 38.73% respectively. The improved matching characteristic of proposed structure is believed to be mainly due to the decreased distance between two emitters of pair BJTs, which results in the decreased effect of deep n-well of which resistance has the higher standard deviation than the other resistances.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.50 no.1
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• pp.17-22
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• 2001

The floating-gate MOSFETs were fabricated by employing 1.5 m n-well CMOS process and their optical-electrical properties were characterized for the application to CMOS image sensor system. Based on the simulation of energy band diagram and operating mechanism of parasitic BJT were proposed as solutions for the increase of photo-current value. In order to realize them, MOSFETs having multi-gate and channel structures were fabricated and 60% increase in photo-current was achieved through enlargement of depletion layer and parallel connection of parasitic BJTs by channel division.

• Journal of IKEEE
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• v.25 no.4
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• pp.735-740
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• 2021

In this paper, we propose a new ESD protection device with high holding voltage with low current gain of parasitic NPN BJT by improving the structure of the existing LTDDSCR. The electrical characteristics of the proposed protection device were analyzed by HBM simulation using Synopsys' TCAD simulation, and the operation of the added BJT was confirmed by current flow, impact ionization and recombination simulation. In addition, the holding voltage characteristics were optimized with the design variables D1 and D2. As a result of the simulation, it was verified that the new ESD protection device has a higher holding voltage compared to the existing LTDDSCR and has a symmetrical bidirectional characteristic. Therefore, the proposed ESD protection device has high area efficiency when applied to an IC and is expected to improve the reliability of the IC.

• Journal of IKEEE
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• v.22 no.1
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• pp.80-86
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• 2018

In this paper, we propose a new PNP bipolar insertion type ESD protection circuit with improved electrical characteristics than the existing ESD protection circuits SCR and LVTSCR. The proposed circuit has 8.59V trigger voltage which is about 9V lower than that of the conventional SCR, and the parasitic PNP has one more operation and high robustness characteristics. For the practical design of the proposed ESD protection circuit, the holding voltage was increased by increasing the base length of the parasitic PNP while increasing the variable L. To verify the electrical characteristics of the proposed device, Synopsys T-CAD simulator was used.

• Journal of IKEEE
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• v.23 no.1
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• pp.338-341
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• 2019

In this paper, we propose a novel ESD device with improved characteristics of LVTSCR, which is a representative ESD protection device, and verify the N-stack technology for design optimized for each required voltage of a specific application. The characteristics of the holding voltage and the trigger voltage, which are the main parameters, are examined and the temperature characteristic, which is an indicator of the tolerance characteristic, is also verified. well region and a parasitic NPN to form a series-connected structure. We used synopsys' T-cad simulation tool for characterization.

• Journal of IKEEE
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• v.26 no.3
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• pp.520-523
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• 2022

In this paper, an ESD protection device with a simpler structure than the existing ESD protection device is proposed. The proposed new structure operates an additional NPN parasitic bipolar transistor by adding an N+ diffusion region and connecting it to the bridge region, thereby lowering the current gain. As a result, it was confirmed that the proposed ESD protection device has a trigger voltage of 10.8V and a holding voltage of 6.1V. It is expected to have reliability for 5V applications and is expected to have high tolerance characteristics.

• Journal of IKEEE
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• v.26 no.1
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• pp.119-123
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• 2022

This paper propose a new ESD protection device suitable for 12V class applications by adding a self-biasing structure to an ESD protection device with high holding voltage due to additional parasitic bipolar BJT. To verify the operating principle and electrical characteristics of the proposed device, current density simulation and HBM simulation were performed using Synopsys' TCAD Simulation, and the operation of the additional self-biasing structure was confirmed. As a result of the simulation, it was confirmed that the proposed ESD protection device has a higher level of holding voltage compared to the existing ESD protection device. It is expected to have high area efficiency due to the dual structure and sufficient latch-up immunity in 12V-class applications.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.12
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• pp.194-200
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• 2012

In this paper, we proposed a SPICE model of high-voltage insulated gate bipolar transistor(IGBT). The proposed model consists of two sub-devices, a MOSFET and a BJT. Basic I-V characteristics and their temperature dependency were realized by adjusting various parameters of the MOSFET and the BJT. To model nonlinear parasitic capacitances such as a reverse-transfer capacitance, multiple junction diodes, ideal voltage and current amplifiers, a voltage-controlled resistor, and passive devices were added in the model. The accuracy of the proposed model was verified by comparing the simulation results with the experimental results of a 1200V trench gate IGBT.