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A study on the Design of NPN BJT built-in SCR for Low Voltage Class ESD Protection

저전압급 ESD 보호를 위한 NPN BJT 내장형 SCR 설계에 관한 연구

  • Received : 2022.09.09
  • Accepted : 2022.09.20
  • Published : 2022.09.30

Abstract

In this paper, an ESD protection device with a simpler structure than the existing ESD protection device is proposed. The proposed new structure operates an additional NPN parasitic bipolar transistor by adding an N+ diffusion region and connecting it to the bridge region, thereby lowering the current gain. As a result, it was confirmed that the proposed ESD protection device has a trigger voltage of 10.8V and a holding voltage of 6.1V. It is expected to have reliability for 5V applications and is expected to have high tolerance characteristics.

본 논문에선 기존의 ESD 보호소자보다 간단한 구조의 ESD 보호소자를 제안하였다. 제안하는 새로운 구조는 N+확산영역을 추가하고 브릿지영역과 연결함으로써 추가 NPN 기생 바이폴라 트랜지스터를 동작시켜 전류이득을 낮춘다. 그 결과 제안된 ESD 보호소자는 10.8V의 트리거 전압 및 6.1V의 홀딩전압을 갖는 것을 확인하였다. 이는 5V 어플리케이션에 신뢰성을 가질 것으로 기대되며 높은 감내특성을 가질 것으로 예상된다.

Keywords

Acknowledgement

This paper was supported by Korea Evaluation Institute of Industrial Technology(KEIT) grant funded by the Ministry of Trade, Industry & Energy (20016115, "Development of DLDO with 99% maximum current efficiency of event-driven asynchronous type without external capacitor") and RS-2022-00143842, "Single/Three-phase AC/DC Converter Smart Power IC using SiC MOSFET devices"

References

  1. Albert Z,H. Wang, On-Chip ESD Protection for Integrated devices 2nd edition Springer, US,2002.
  2. M.-D. Ker and C.-C. Yen, "Investigation and design of on-chip power rail ESD clamp circuits without suffering latchup-like failure during system-level ESD test," IEEE J. Solid-State Circuits, vol.43, no.11, pp.2533-2345, 2008. DOI: 10.1109/JSSC.2008.2005451
  3. O. Semenov, H. Sarbishaei, and M. Sachdev, "ESD protection design for advanced CMOS," in Proc. SPIE, pp.123-131, 2001. DOI: 10.1007/978-1-4020-8301-3
  4. Y. Koo, K. Lee, K. Kim, and J. Kwon, "Design of SCRbased ESD protection device for power clamp using deepsubmicron CMOS technology," Microelectron. J., vol.40, no.6, pp.1007-1012, 2009. DOI: 10.1016/j.mejo.2009.01.001
  5. R. G. Wagner, J. Soden, and C. F. Hawkins, "Extend and cost of EOS/ESD damage in an IC manufacturing process," in Proc. EOS/ESD Symp., pp.49-55, 1993.
  6. M.-D. Ker and C.-C. Yen, "Investigation and design of on-chip powerrail ESD clamp circuits without suffering latchup-like failure during systemlevel ESD test," IEEE J. Solid-State Circuits, vol.43, no.11, pp.2533-2545, 2008. DOI: 10.1109/JSSC.2008.2005451