Fig. 1. Cross sectional view of LVTSCR. 그림 1. LVTSCR의 단면도
Fig. 2. Equivalent circuit of LVTSCR. 그림 2. LVTSCR의 등가회로
Fig. 3. Cross sectional view of Proposed Device. 그림 3. 제안된 소자의 단면도
Fig. 4. Equivalent circuit of Proposed Device. 그림 4. 제안된 소자의 등가회로
Fig. 5. Cross sectional view of N-stacked LVTSCR. 그림 5. N-stack 기술을 적용한 LVTSCR의 단면도
Fig. 6. Cross sectional view of N-stacked Proposed Device. 그림 6. N-stack 기술을 적용한 제안된 소자의 단면도
Fig. 7. IV-Curve of LVTSCR and Proposed Device. 그림 7. LVTSCR과 제안된 소자의 IV-Curve
Fig. 8. HBM-4K Temperature Characteristic of LVTSCR and Proposed Device. 림 8. LVTSCR과 제안된 소자의 HBM-4K 온도 특성
Fig. 9. IV-Curve of Device with N-stack technology. 그림 9. N-stack 기술이 적용된 소자의 IV-Curve
Table 1. Trigger voltage and Holding voltage measurement results for each structure. 표 1. 각 구조별 트리거전압과 홀딩전압 측정결과
Table 2. HBM-4K Temperature measurement results for each structure. 표 2. 각 구조별 HBM-4K 온도측정 결과
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