• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.11
• /
• pp.9-16
• /
• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• The Journal of the Acoustical Society of Korea
• /
• v.24 no.1
• /
• pp.11-20
• /
• 2005

In this paper, we deal with the research about a S/PDIF (Sony Philips Digital Interface) receiver which can operate without PLL (Phase Locked Loop) circuits. Although a S/PDIF receiver is used in most audio devices and audio processors in these days. yet there are only few domestic researches about S/PDIF. Currently used commercial DACs (Digital-to-Analog Converters) which can decode S/PDIF signals, have a PLL circuit inside them. The PLL makes it possible to extract clock information from S/PDIF digital signal and to synchronize a clock signal with input signals. But the PLL circuit makes many diffculties in designing the SOC (System On Chips) of VLSIs (Vew Large Scale Integrated Ciruits) because it is an "analog circuit". We proposed a S/PDIF receiver which doesn't have PLL circuits and only has Pure digital circuits. The key idea of the proposed S/PDIF receiver. is to use the ratio between a 16 MHz basic input clock and S/PDIF signals. After having decoded hundreds thousands S/PDIF inputs, it went to prove that a S/PDIF receiver can be designed with pure digital circuits and without any analog circuits such as PLL circuits. We have confidence that the proposed S/PDIF receiver can be used as an IP (Intellectual Property) for the SOC design of the digital circuits.

• Proceedings of the KIPE Conference
• /
• 2013.11a
• /
• pp.256-257
• /
• 2013

계통 연계형 시스템에서 왜곡된 입력전압에 대해서 기본파 전압의 크기, 주파수, 위상 등을 정확히 추종함으로써 계통과 시스템 간의 빠르고 정확한 동기화 과정은 매우 중요하다. 본 논문은 불평형 및 고조파를 포함한 3상 전압 조건에서 기본파 성분의 위상 추출을 위한 두 가지 기법인 Time Delay PLL과 MDSOGI PLL기법을 Matlab Simulink를 통해 모델링하고 비교 분석 하였다. 동기좌표계에서 발생되는 고조파 성분의 영향을 저감시키는 효과를 확인하고 그 특성을 비교하였다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2000.10a
• /
• pp.485-489
• /
• 2000

본 논문에서는 단일 PLL을 사용하여 400MHz 대역의 트랜시버를 구현하였다. 일반적인 트랜시버의 경우, 송수신부에 각각 한 개의 PLL과 수신부에 2단의 믹서를 사용하여 구현되어진다. 이러한 구성은 트랜시버의 가격과, 부피에 상당히 큰 영향을 미친다. 본 논문에서는 기존의 방식을 탈피하여 단일 PLL방식의 데이터 전송용 특정 소출력 무선기기의 송, 수신단의 회로설계, 제작 및 특성측정을 하였다. 설계된 트랜시버의 주파수 대역은 424.7-424.95MHz이고, Low Side Injection방식을 사용하여 450KHz의 If 주파수로 변환(Conversion)하였고, 반이중(Semi duplex Communication) 통신방식, PLL Synthesized, 21 Channel, 12.5KHz Channel BandwidttL FSK Modulation / Demodulation 방식을 사용하였다.

• Proceedings of the KIEE Conference
• /
• 2006.10c
• /
• pp.479-481
• /
• 2006

This paper describes a 2.5V, 320MHz low-noise and low-power Phase Locked Loop(PLL) using a noise-rejected Voltage Controlled ring Oscillator(VCO) fabricated in a TSMC 0.25um CMOS technology. In order to improve the power consumption and oscillation frequency of the PLL, The VCO consist of three-stage fully differential delay cells that can obtain the characteristic of high speed, low power and low phase noise. The VCO operates at 7MHz -670MHz. The oscillator consumes l.58mA from a 320MHz frequency and 2.5V supply. When the PLL with fully-differential ring VCO is locked 320MHz, the jitter and phase noise measured 26ps (rms), 157ps (p-p) and -97.09dB at 100kHz offset. We introduce and analysis the conditions in which ring VCO can oscillate for low-power operation.

• 전자공학회논문지 IE
• /
• v.46 no.1
• /
• pp.1-6
• /
• 2009

This paper presents the digital PLL architecture and design for improving the frequency detection range and locking time for wide-band frequency synthesizer applications. In this research, a wide-range digital logic quadricorrelator is used for wide-band and fast frequency detector and sigma-delta modulator with 2-bit up-down counter is adopted for DCO control. The proposed digital PLL reduces the phase noise from quantization effect and is suitable for implementation of wide-band fast-locking as well as low power features, which is in high demand for mobile multimedia applications.

• ETRI Journal
• /
• v.29 no.4
• /
• pp.463-469
• /
• 2007

A phase-locked loop (PLL) is described which is operable from 0.4 GHz to 1.2 GHz. The PLL has basically the same architecture as the conventional analog PLL except the locking information is stored as digital code. An analog-to-digital converter is embedded in the PLL, converting the analog loop filter output to digital code. Because the locking information is stored as digital code, the PLL can be turned off during power-down mode while avoiding long wake-up time. The PLL implemented in a 0.18 ${\mu}m$ CMOS process occupies 0.35 $mm^2$ active area. From a 1.8 V supply, it consumes 59 mW and 984 ${\mu}W$ during the normal and power-down modes, respectively. The measured rms jitter of the output clock is 16.8 ps at 1.2 GHz.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.7 no.4
• /
• pp.241-246
• /
• 2007

This paper presents two novel compensation circuits for leakage current and power supply noise (PSN) in phase locked loop (PLL) using a nanometer CMOS technology. The leakage compensation circuit reduces the leakage current of the charge pump circuit and the PSN compensation circuit decreases the effect of power supply variation on the output frequency of VCO. The PLL design is based on a 32nm predictive CMOS technology and uses a 0.9 V power supply voltage. The simulation results show that the proposed PLL achieves 88% jitter reduction at 440 MHz output frequency compared to the PLL without leakage compensator and its output frequency drift is little to 20% power supply voltage variations. The PLL has an output frequency range of 40 $M{\sim}725$ MHz with a multiplication range of 1-1023, and the RMS and peak-to-peak jitter are 5psec and 42.7 psec, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2008.06a
• /
• pp.533-534
• /
• 2008

This paper presents a multi-phase ring VCO for low-cost, low-power GPS receiver. In the RF band used in GPS, L1 band is now in commercial-use and L2,L5 are predicting to be commercial-use soon. Thus Wide band PLL and Cost-effective IC solutions are required for future multi-band GPS receiver that received three types band at once. A new PLL architecture for multi-band GPS application is proposed. Ring VCO is even smaller than LC-VCO and a good alternative for low-cost solution. Proposed multi-phase ring VCO offers wide frequency range covering L1, L2, and L5 band, 20% reduction of area, 23% reduction of PLL power and can generate I/Q without extra I/Q generator.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2016.05a
• /
• pp.154-156
• /
• 2016

In this paper, the proposed small size PLL works stable with the discrete loop filter which is controlled by voltage controlled oscillator's output signal. Sampling and a small size capacitor functioned negative feedback with switch does make it possible to integrate the PLL into a single chip. The proposed PLL is designed by 1.8V 0.18um CMOS process.