• 대한전기학회:학술대회논문집
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• 대한전기학회 1997년도 하계학술대회 논문집 C
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• pp.1270-1273
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• 1997

We have investigated the latchup characteristics of BL/BILLI retrograde twin well CMOS that has the high energy ion implanted buried layer to intend for more improvement of latchup compare to conventional retrograde well and BILLI structures. We explored the dependence of various latchup characteristics such as n+ trigger latchup and p+ trigger latchup on the buried layer implant doses. We show various DC latchup characteristics that allow us to evaluate each technology and suggest guidelines for the reduction of latchup susceptibility.

• 한국정보통신학회논문지
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• 제18권12호
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• pp.3079-3084
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• 2014

펄스 방사선에 의해 전자소자가 받는 영향으로는 Upset, Latchup, Burnout 등이 있다. 이 가운데 Latchup은 대상 소자에 회복 불가능한 영구손상(Permanent Damage)을 가져오게 되며 Burnout으로도 이어져 장비전체에 치명적 기능마비를 유발하기도 한다. 본 연구에서는 전자소자의 내부 공정설계 및 구조정보 활용이 불가능한 상황에서 실험을 통해서 펄스 방사선에 의한 Latchup 발생을 분석하고자 시도하였다. 소자를 전자빔변환 고준위 펄스 감마선 조사한 직후 수행한 전원제공 회로의 차단, 적외선 카메라의 열원측정, 그리고 손상발생 소자의 내부 회로분석의 세 단계별 확인과정은 펄스 방사선에 의해 유발된 Latchup임을 검증하는 효율적 방안으로 여겨진다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.1553-1555
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• 1996

This paper deals with latchup effect in CMOS retrograde well, focusing on their dependence on I/I energy conditions, so we derived some latchup characteristics from simulation for different I/I conditions on implantation energies which were used in process simulation. From these results, we could understand the dependency of CMOS retrograde well latchup on I/I energy condition.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.1185-1186
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• 2008

A nuclear explosion emits a transient radiation pulse like gamma rays. Gamma rays have a high energy and cause unexpected effects in semiconductor devices. These effects are mainly referred to dose-rate latcup and dose-rate upset. By transient radiation pulse in CMOS devices, dose-rate latchup is simulated in this paper.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1372-1373
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• 2006

An electrostatic discharge (ESD) protection device, so called, N-type SCR with P-type MOSFET pass structure (NSCR_PPS), was analyzed for high voltage I/O applications. A conventional NSCR_PPS device shows typical SCR-like characteristics with extremely low snapback holding voltage, which may cause latchup problem during normal operation. However, a modified NSCR_PPS device with proper junction/channel engineering demonstrates highly latchup immune current- voltage characteristics.

• 한국전기전자재료학회논문지
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• 제13권2호
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• pp.106-113
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• 2000

This study describes how a properly calibrated simulation method could be used to investigate the latchup immunity characteristics among the various high energy ion implanted CMOS twin well (retro-grade/BILLI/BL) structures. To obtain the accurate quantitative simulation analysis of retrograde well, a global tuning procedure and a set of grid specifications for simulation accuracy and computational efficiency are carried out. The latchup characteristics of BILLI and BL structures are well predicted by applying a calibrated simulation method for retrograde well. By exploring the potential contour, current flow lines, and electron/hole current densities at the holding condition, we have observed that the holding voltage of BL structure is more sensitive to the well design rule (p+to well edge space /n +to well edge space) than to the retrograde well itself.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.227-231
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• 2008

A latchup-free design based on the lateral diffused MOS (LDMOS) adopting the "Darlington" approaches was designed. The use of Darlington configuration as the trigger circuit results in the reduction of the size of the circuit when compared to the conventional inverter driven RC-triggered MOSFET ESD power clamp circuits. The proposed clamp was fabricated using a $0.35{\mu}m$ 60V BCD (Bipolar CMOS DMOS) process and the performance of the proposed clamp was successfully verified by TLP (Transmission Line Pulsing) measurements.

• 전자공학회논문지A
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• 제30A권7호
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• pp.32-37
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• 1993

A novel insulated gate bipolar transister (IGBT), called insulated trench cathode IGBT (ISTC-IGBT), is proposed. ISTC-IGBT has a trenched well with the shallow P$^{+}$ juction in the conventional IGBT structure. The proposed structure has the capability of effectively suppressing the parasitic thyristor latchup. The holding current of ISTC-IGBT is about 2.2 times greater than that of the conventional IGBT. Detailed analysis of the latchup characteristics of ISTC-IGBT is performed by using the two-dimensional device simulator, PISCES-II B.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1370-1371
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• 2006

An electrostatic discharge (ESD) protection device, so called, N-type extended drain silicon controlled rectifier (NEDSCR) device, was analyzed for high voltage I/O applications. A conventional NEDSCR device shows typical SCR-like characteristics with extremely low snapback holding voltage. This may cause latchup problem during normal operation. However, a modified NEDSCR device with proper junction / channel engineering demonstrates itself with both the excellent ESD protection performance and the high latchup immunity.

• 한국위성정보통신학회논문지
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• 제7권2호
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• pp.18-24
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• 2012

본 논문에서는 ESD 방지를 위한 최적 방법론에 목표하여 확장된 드레인을 갖는 EDNMOS 소자의 더블 스냅백 현상 및 백그라운 도핑 농도 (BDC)의 영향을 조사하였다. 고전류 영역에서 낮은 BDC를 가진 EDNMOS 소자는 강한 스냅백으로 인해 취약한 ESD 성능과 높은 래치업 위험을 가지게 되나, 높은 BDC를 가진 EDNMOS 소자는 스냅백을 효과적으로 방지할 수 있음을 알 수 있었다. 따라서 BDC 제어로 안정적인 ESD 방지 성능과 래치업 면역을 구현할 수 있음을 밝혔다.