대한전기학회:학술대회논문집 (Proceedings of the KIEE Conference)
- 대한전기학회 1996년도 하계학술대회 논문집 C
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- Pages.1553-1555
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- 1996
CMOS Well의 Ion Implantation 공정조건에 따른 Latchup 면역성 모의실험
Latchup Immunity Simulation of CMOS Well for Ion Implantation Process Simulation Conditions
- 김종관 (고려대학교 공과대학 전기공학과) ;
- 이진우 (고려대학교 공과대학 전기공학과) ;
- 김영훈 (고려대학교 공과대학 전기공학과) ;
- 김태훈 (고려대학교 공과대학 전기공학과) ;
- 성영권 (고려대학교 공과대학 전기공학과)
- Kim, J.K. (Dept. of Electrical Eng. Korea University) ;
- Yi, J.W. (Dept. of Electrical Eng. Korea University) ;
- Kim, Y.H. (Dept. of Electrical Eng. Korea University) ;
- Kim, T.H. (Dept. of Electrical Eng. Korea University) ;
- Sung, Y.K. (Dept. of Electrical Eng. Korea University)
- 발행 : 1996.07.22
초록
This paper deals with latchup effect in CMOS retrograde well, focusing on their dependence on I/I energy conditions, so we derived some latchup characteristics from simulation for different I/I conditions on implantation energies which were used in process simulation. From these results, we could understand the dependency of CMOS retrograde well latchup on I/I energy condition.
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