• Proceeding of EDISON Challenge
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• 2017.03a
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• pp.499-505
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• 2017

Photoisomerizing molecules which can transform their structure by the light irradiation have great deal for the application of photo-switching devices. And azobenzene is the representive type of the photoisomerizing molecules. It can transform their trans- structures into cis- structure as the light for certain wave lengths they receive. This property shows the potential of ON/OFF switching functionalization which can be used into the nano scale photo switch. Furthermore, many studies are interested in the organic linkers that connect the azobenzene and metal electrodes. We used S, $CH_2S$, $(CH_2)_4S$ as the linker to watch the influence of linkers for electronic properties. So We suggest a photoswitching device based on the vertical junction using the first-principles calculations with density functional theory and non-equilibrium Greens function (NEGF). By analyzing the electronic structure and tunneling current caused by the structural difference of the system between cis- and trans- azobenzene, the difference in switching mechanism, ON/OFF ratio and transmission will be watched as the linker changes. And finally We will suggest which linker would be the better for the optimal device architecture which can achieve high control of the ON/OFF photocurrent ratio. This result will show the potential of azobenzene-based photoswitch and provide the critical insight in constructing the optimal device architecture.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.25 no.3
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• pp.165-169
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• 2012

Power semiconductor devices are widely used as high voltage applications to inverters and motor drivers, etc. The blocking voltage is one of the most important parameters for power semiconductor devices. And cause of junction curvature effects, the breakdown voltage of the device edge and device unit cells was found to be lower than the 'ideal' breakdown voltage limited by the semi-infinite junction profile. In this paper, Propose the methods for field ring design by DOE (Design of Experimentation). So The field ring can be improve for breakdown voltage and optimization.

• Journal of Satellite, Information and Communications
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• v.8 no.2
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• pp.36-43
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• 2013

In this study, the high current behaviors and double snapback mechanism of gate grounded_extended drain n-type MOSFET(GG_EDNMOS) device were analyzed in order to realize the robust electrostatic discharge(ESD) protection performances of high voltage operating display driver IC(DDIC) chips. Both the transmission line pulse(TLP) data and the thermal incorporated 2-dimensional simulation analysis as a function of ion implant conditions demonstrate a characteristic double snapback phenomenon after triggering of bipolar junction transistor(BJT) operation. Also, the background carrier density is proven to be a critical factor to affect the high current behavior of the GG_EDNMOS devices.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.12
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• pp.80-90
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• 1994

To develop VLSI of higher packing density with 0.5.mu.m gate length of less, semiconductor devices require shallow junction with higher doping concentration. the most common method to form the shallow junction is ion implantation, but in order to remove the implantation induced defect and activate the implanted impurities electrically, ion-implanted Si should be annealed at high temperature. In this annealing, impurities are diffused out and redistributed, creating deep PN junction. These make it more difficult to form the shallow junction. Accordingly, to miimize impurity redistribution, the thermal-budget should be kept minimum, that is. RTA needs to be used. This paper reports results of the diffusion characteristics of PSG film by varying Phosphorus weitht %/ Times and temperatures of RTA. From the SIMS.ASR.4-point probe analysis, it was found that low sheet resistance below 100 .OMEGA./ㅁand shallow junction depths below 0.2.mu.m can be obtained and the surface concentrations are measured by SIMS analysis was shown to range from 2.5*10$^{17}$ aroms/cm$^{3}$~3*10$^{20}$ aroms/cm$^{3}$. By depending on the RTA process of PSG film on Si, LDD-structured nMOSFET was fabricated. The junction depths andthe concentration of n-region were about 0.06.mu.m. 2.5*10$^{17}$ atom/cm$^{-3}$ , 4*10$^{17}$ atoms/cm$^{-3}$ and 8*10$^{17}$ atoms/cm$^{3}$, respectively. As for the electrical characteristics of nMOS with phosphorus junction for n- region formed by RTA, it was found that the characteristics of device were improved. It was shown that the results were mainly due to the reduction of electric field which decreases hot carriers.

• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1448-1450
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• 1994

The breakdown voltages of punchthrough-mode diodes with cylindrical junction are analytically calculated, The proposed method, which is based on th Gauss's law, estimates the lateral expansion of the depletion region as well as the electric field and the charge distribution. The proposed method is given in terms of epitaxial layer width, the epitaxial layer doping concentration, and curvature radius of the junction edge. The calculation results agree well with the MEDICI simulation results for various device parameters.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.29 no.11 s.242
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• pp.1503-1508
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• 2005

Scanning Thermal Microscope (STU) has been known for its superior resolution for local temperature and thermal property measurement. However, commercially available STU probe which is the key component of SThM does not provide resolution enough to explore nanoscale thermal phenomena. Here, we developed a SThM probe fabrication process that can achieve spatial resolution around 50 m. The batch-fabricated probe has a thermocouple junction located at the end of the tip. The size of the thermocouple junction is around 200 m and the distance of the junction from the very end of the tip is 150 m. The probe is currently being used for nanoscale thermal probing of nano-material and nano device.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2007.06a
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• pp.109-112
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• 2007

In this paper we describe a robust method of improving precision in monitoring high energy ion implantation processes. Ion implant energy accuracy was measured in the device manufacturing process using an unpatterned implanted layer on an intrinsic p-type silicon wafer. To increase Rs sensitivity to energy at the well implant process, a PN junction structure was formed by P-well and deep N-well implants into the p-type Si wafer. It was observed that the depletion layer formed by the PN junction was very sensitive to energy variation of the well implant. Conclusively, it can be recommended to monitor well implant processes using the Rs measurement method described herein, i.e., a PN junction diode structure since it shows excellent Rs sensitivity to variation caused by energy difference at the well implant step.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.237-240
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• 2002

In this W, a NiSi technology suitable for sub-100nm CMOS sevice is proposed. It seems that capping layer has little effect on the sheet resistance and junction leakage current when there is no thermal treatment. However, there happened agglomeration and drastic increase of Junction leakage current without capping layer. In other word, capping layer especially TiN capping layer is highly effective in suppressing thermal effect. It is shown that the sheet resistance of 0.12${\mu}{\textrm}{m}$ linewidth and shallow p+/n junction with NiSi were stable up to 700 t /30 minute thermal treatment.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.241-244
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• 2000

To investigate the compact effect of the different area of an active layer and the different type of heatsink on the junction to ambient transient thermal impedance, we have characterized the thermal behavior of power MOSFETs that have three different areas of an active layer and two types of heatsink. To do so, the "cooling curve method" has been used in order to measure the junction-to-ambient transient thermal impedance Zthja that represents the thermal behavior of the devices. The measured data depiets that the larger area of an active layer gives the better-in other words. smaller-thermal impedance, and that the larger size of a heatsink improves the thermal impedance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.1
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• pp.16-21
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• 2006

A simple doping method to fabricate a very thin channel body of the p-type FinFETs with a 20 nm gate length by solid-phase-diffusion (SPD) process was developed. Using the poly-boron-films (PBF) as a novel diffusion source of boron and the rapid thermal annealing (RTA), the p-type sourcedrain extensions of the FinFET devices with a threedimensional structure were doped. The junction properties of boron doped regions were investigated by using the $p^+-n$ junction diodes which showed excellent electrical characteristics. Single channel and multi-channel p-type FinFET devices with a gate length of 20-100 nm was fabricated by boron diffusion process using PBF and revealed superior device scalability.