• Title/Summary/Keyword: IEEE 1149.1

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A Design of Instruction Based Wrapped Core Linking Module for Hierarchical SoC Test Access (계층적 SoC 테스트 접근을 위한 명령어 기반 코아 연결 모듈의 설계)

  • Yi Hyun-Bean;Park Sung-Ju
    • The Transactions of the Korean Institute of Electrical Engineers D
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    • v.52 no.3
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    • pp.156-162
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    • 2003
  • For a System-on-a-Chip(SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper, we introduce a new instruction based Wrapped Core Linking Module(WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cotes and P1500 wrapped cores with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.

At-speed Interconnect Test Controller for SoC with Multiple System Clocks and Heterogeneous Cores (다중 시스템 클럭과 이종 코아를 가진 시스템 온 칩을 위한 연결선 지연 고장 테스트 제어기)

  • Jang Yeonsil;Lee Hyunbin;Shin Hyunchul;Park Sungju
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.5 s.335
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    • pp.39-46
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    • 2005
  • This paper introduces a new At-speed Interconnect Test Controller (ASITC) that can detect and diagnose dynamic as well as static defects in an SoC. SoC is comprised of IEEE 1149.1 and P1500 wrapped cores which can be operated by multiple system clocks. In other to test such a complicated SoC, we designed a interface module for P1500 wrapped cores and the ASITC that makes it possible to detect interconnect delay faults during 1 system clock from launching to capturing the transition signal. The ASITC proposed requires less area overhead than other approaches and the operation was verified through the FPGA implementation

A Boundary-Scan Based On-Line Circuit Performance Monitoring Scheme (경계 스캔 기반 온-라인 회로 성능 모니터링 기법)

  • Park, Jeongseok;Kang, Taegeun;Yi, Hyunbean
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.1
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    • pp.51-58
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    • 2016
  • As semiconductor technology has developed, device performance has been improved. However, since device structures became smaller, circuit aging due to operational and environmental conditions can be accelerated. Circuit aging causes a performance degradation and eventually a system error. In reliable systems, a failure due to aging might cause a great disaster. Therefore, these systems need a performance degradation prediction function so that they can take action in advance before a failure occurs. This paper presents an on-line circuit performance degradation monitoring scheme for predicting a failure by detecting performance degradation during circuit normal operation. In our proposed scheme, IEEE 1149.1 output boundary scan cells and TAP controller are reused. The experimental result shows that the proposed architecture can monitor the performance degradation during normal operation without stopping the circuit.

IEEE 1500 Wrapper and Test Control for Low-Cost SoC Test (저비용 SoC 테스트를 위한 IEEE 1500 래퍼 및 테스트 제어)

  • Yi, Hyun-Bean;Kim, Jin-Kyu;Jung, Tae-Jin;Park, Sung-Ju
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.44 no.11
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    • pp.65-73
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    • 2007
  • This paper introduces design-for-test (DFT) techniques for low-cost system-on-chip (SoC) test. We present a Scan-Test method that controls IEEE 1500 wrapper thorough IEEE 1149.1 SoC TAP (Test Access Port) and design an at-speed test clock generator for delay fault test. Test cost can be reduced by using small number of test interface pins and on-chip test clock generator because we can use low-price automated test equipments (ATE). Experimental results evaluate the efficiency of the proposed method and show that the delay fault test of different cores running at different clocks test can be simultaneously achieved.

An Extended Scan Path Architecture Based on IEEE 1149.1 (IEEE 1149.1을 이용한 확장된 스캔 경로 구조)

  • Son, U-Jeong;Yun, Tae-Jin;An, Gwang-Seon
    • The Transactions of the Korea Information Processing Society
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    • v.3 no.7
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    • pp.1924-1937
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    • 1996
  • In this paper, we propose a ESP(Extended Scan Path) architecture for multi- board testing. The conventional architectures for board testing are single scan path and multi-scan path. In the single scan path architecture, the scan path for test data is just one chain. If the scan path is faulty due to short or open, the test data is not valid. In the multi-scan path architecture, there are additional signals in multi-board testing. So conventional architectures are not adopted to multi-board testing. In the case of the ESP architecture, even though scan paths either short or open, it doesn't affect remaining other scan paths. As a result of executing parallel BIST and IEEE 1149.1 boundary scan test by using, he proposed ESP architecture, we observed to the test time is short compared with the single scan path architecture. Because the ESP architecture uses the common bus, there are not additional signals in multi-board testing. By comparing the ESP architecture with conventional one using ISCAS '85 bench mark circuit, we showed that the architecture has improved results.

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A Study on Built-In Self Test for Boards with Multiple Scan Paths (다중 주사 경로 회로 기판을 위한 내장된 자체 테스트 기법의 연구)

  • Kim, Hyun-Jin;Shin, Jong-Chul;Yim, Yong-Tae;Kang, Sung-Ho
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.2
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    • pp.14-25
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    • 1999
  • The IEEE standard 1149.1, which was proposed to increase the observability and the controllability in I/O pins, makes it possible the board level testing. In the boundary-scan environments, many shift operations are required due to their serial nature. This increases the test application time and the test application costs. To reduce the test application time, the method based on the parallel opereational multiple scan paths was proposed, but this requires the additional I/O pins and the internal wires. Moreover, it is difficult to make the designs in conformity to the IEEE standard 1149.1 since the standard does not support the parallel operation of data shifts on the scan paths. In this paper, the multiple scan path access algorithm which controls two scan paths simultaneously with one test bus is proposed. Based on the new algorithm, the new algorithm, the new board level BIST architecture which has a relatively small area overhead is developed. The new BIST architecture can reduce the test application time since it can shift the test patterns and the test responses of two scan paths at a time. In addition, it can reduce the costs for the test pattern generation and the test response analysis.

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An Efficient SoC Test Architecture for Testing Various Cores in Parallel (다양한 코어의 병렬 테스트를 지원하는 효과적인 SOC 테스트 구조)

  • Kim, Hyun-Sik;Kim, Yong-Joon;Park, Hyun-Tae;Kang, Sung-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.43 no.10 s.352
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    • pp.140-150
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    • 2006
  • In this paper, we present a new hardware architecture for testing various cores embedded in SoC. The conventional solutions need much testing time since only one core is tested at single test period. To enhance this, S-TAM, a novel test architecture, and its controller which enable parallel testing of various cores are proposed. S-TAM supports bus sharing to broadcast testing and cores to be tested are selected by using it. In addition, S-TAM controller enables the effective SoC test by simultaneous controlling the various test cores which are based on the different test architectures like IEEE 1149.1 and IEEE 1500.

A New Key Protection Technique of AES Core against Scan-based Side Channel Attack (스캔 기반 사이드 채널 공격에 대한 새로운 AES 코아 키 보호 기술)

  • Song, Jae-Hoon;Jung, Tae-Jin;Park, Sung-Ju
    • Journal of KIISE:Computer Systems and Theory
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    • v.36 no.1
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    • pp.33-39
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    • 2009
  • This paper presents a new secure scan design technique to protect secret key from scan-based side channel attack for an Advanced Encryption Standard(AES) core embedded on an System-on-a-Chip(SoC). Our proposed secure scan design technique can be applied to crypto IF core which is optimized for applications without the IP core modification. The IEEE1149.1 standard is kept, and low area and power consumption overheads and high fault coverage can be achieved compared to the existing methods.

Memory BIST Circuit Generator System Design Based on Fault Model (고장 모델 기반 메모리 BIST 회로 생성 시스템 설계)

  • Lee Jeong-Min;Shim Eun-Sung;Chang Hoon
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.2 s.332
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    • pp.49-56
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    • 2005
  • In this paper, we propose a memory BIST Circuit Creation System which creates BIST circuit based on user defined fault model and generates the optimized march test algorithm. Traditional tools have some limit that regenerates BIST circuit after changing the memory type or test algorithm. However, this proposed creation system can automatically generate memory BIST circuit which is suitable in the various memory type and apply algorithm which is required by user. And it gets more efficient through optimizing algorithms for fault models which is selected randomly according to proposed nile. In addition, it support various address width and data and consider interface of IEEE 1149.1 circuit.

Development of Simple Reconfigurable Access Mechanism for SoC Testing (재구성 가능한 시스템 칩 테스트 제어기술의 개발)

  • 김태식;민병우;박성주
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.41 no.8
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    • pp.9-16
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    • 2004
  • For a System-on-a-Chip(SoC) comprised of multiple IP cores, test control techniques have been developed to perform the internal and external test efficiently relying on the various design for testability techniques such as scan and BIST(Built-In Self-Test). However the test area overhead is too expensive to guarantee diverse test link configurations. In this paper, at first we introduce a new flag based Wrapped Core Linking Module(WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cores and P1500 wrapped cores. Then a simple test control technique, which can interconnect internal scan chains of different cores, is described with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.