Journal of the Institute of Electronics and Information Engineers (전자공학회논문지)

The Institute of Electronics and Information Engineers (대한전자공학회)
권호 표지
DOI QR코드

DOI QR Code

A Boundary-Scan Based On-Line Circuit Performance Monitoring Scheme

경계 스캔 기반 온-라인 회로 성능 모니터링 기법

  • Park, Jeongseok (Dept. of Computer Engineering, Hanbat National University) ;
  • Kang, Taegeun (Dept. of Computer Engineering, Hanbat National University) ;
  • Yi, Hyunbean (Dept. of Computer Engineering, Hanbat National University)
  • 박정석 (한밭대학교 컴퓨터공학부) ;
  • 강태근 (한밭대학교 컴퓨터공학부) ;
  • 이현빈 (한밭대학교 컴퓨터공학부)
  • Received : 2015.11.19
  • Accepted : 2015.12.28
  • Published : 2016.01.25
Download PDF
⟨ Previous Next ⟩

Abstract

As semiconductor technology has developed, device performance has been improved. However, since device structures became smaller, circuit aging due to operational and environmental conditions can be accelerated. Circuit aging causes a performance degradation and eventually a system error. In reliable systems, a failure due to aging might cause a great disaster. Therefore, these systems need a performance degradation prediction function so that they can take action in advance before a failure occurs. This paper presents an on-line circuit performance degradation monitoring scheme for predicting a failure by detecting performance degradation during circuit normal operation. In our proposed scheme, IEEE 1149.1 output boundary scan cells and TAP controller are reused. The experimental result shows that the proposed architecture can monitor the performance degradation during normal operation without stopping the circuit.

반도체 제조공정의 발달로 칩의 성능은 더욱 향상되었으나 회로가 미세해지고 복잡해져 동작 환경에 의한 회로의 노화가 가속화 될 수 있다. 회로의 노화는 성능 저하로 나타나며, 결과적으로 시스템 오류를 발생 시킬 수 있다. 고신뢰 시스템에서는, 노화로 인한 오류가 큰 재난으로 이어질 수 있으므로, 사고를 예방하기 위한 오류 발생 예측 기술이 필수적이다. 본 논문에서는 회로의 정상동작 중에 성능 저하를 감지하여 오류를 예측 할 수 있는 모니터링 기법을 제시한다. 모니터링을 위한 별도의 회로를 추가하지 않고 경계 스캔 셀과 TAP 제어기를 재활용한 IEEE 1149.1 경계 스캔 기반의 온-라인 성능 저하 모니터링 방법을 제시한다. 시뮬레이션을 통하여 제안하는 성능 저하 모니터링 기법을 검증한다.

Keywords

References

  1. Y. Li, S. Makar, and S. Mitra, "CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns," Proc. Design Automation and Test in Europe, pp. 885-890, Munich, Germany, Mar. 2008.
  2. Y. Sato, S. Kajihara, Y. Miura, T. Yoneda, S. Ohtake, M. Inoue, and H. Fujiwara, "A Circuit Failure Prediction Mechanism (DART) for High Field Reliability," Proc. Int'l Conf. on ASIC, pp. 581-584, Changsha, Hunan, China, Oct. 2009.
  3. H. Inoue, Y. Li, and S. Mitra, "VAST: Virtualization-Assisted Concurrent Autonomous Self-Test," Proc. Int'l Test Conf., pp. 1-10, Santa Clara, CA, USA, Oct. 2008.
  4. Y. Li, O. Mutlu, and S. Mitra, "Operating System Scheduling for Efficient Online Self-Test in Robust Systems," Int'l Conf. on Computer-Aided Desisn, pp. 201-208, San Jose, CA, USA, Nov. 2009.
  5. D. Ernast et al., "Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation," 36th International Symposium on Microarchitecture, pp. 7-18, San Diego, CA, USA, Dec. 2003.
  6. T. Sato and Y. Kunitake, "A Simple Flip-Flop Circuit for Typical-Case Designs for DFM," 8th International Symposium on Quality Electronic Design, pp. 539-544, San Jose, CA, USA, Mar. 2007.
  7. H. Yi, T. Yoneda, and M. Inoue, "A Scan-Based On-Line Aging Monitoring Scheme," Journal of Semiconductor Technology and Science (JSTS), vol. 14, no. 1, pp. 124-130, Feb. 2014. https://doi.org/10.5573/JSTS.2014.14.1.124
  8. J. K. Eitrheim, "Adjustable Duty Cycle Clock Generator," USA. Patent, PN: 5,638,016, June 1997.
  9. M. Karlsson, M. Vesterbacka, and W. Kulesza, "A Non-Overlapping Two-Phase Clock Generator with Adjustable Duty Cycle," Electronic Proc. Nat. Symp. on Microwave Technique and High Speed Electronics, GHz'03, pp. 4-5, Linkoping, Sweden, Nov. 2003.
  10. H. Yi et al., "A Failure Prediction Strategy for Transistor Aging," IEEE Transactions on VLSI Systems, vol. 20, no. 11, pp. 1951-1959, Nov. 2012. https://doi.org/10.1109/TVLSI.2011.2165304
  11. N. Ahmed, M. Tehranipoor, and V. Jayaram, "A Novel Framework for Faster-than-at-Speed Delay Test Considering IR-drop Effects," Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD '06), pp. 198-203, San Jose, CA, USA, Nov. 2006.
  12. F. Firouzi et al., "Re-using BIST for Circuit Aging Monitoring," 20th IEEE European Test Symposium (ETS), pp. 1-2, Cluj-Napoca, Romania, May 2015.
  13. A. Simevski, R. Kraemer, and M. Krstic, "Low-complexity integrated circuit aging monitor," IEEE 14th International Symposium on Design and Diagnostic of Electronic Circuits & Systems (DDECS), pp. 121-125, Cottbus, Germany, Apr. 2011.
  14. J. C. Vazquez et al., "Predictive Error Detection by On-line Aging Monitoring," IEEE 16th International On-Line Testing Symposium (IOLTS), pp. 9-14, Corfu, Greece, July 2010.
  15. J. C. Vazquez et al., "Built-In Aging Monitoring for Safety-Critical Applications," 15th IEEE International On-Line Testing Symposium (IOLTS 2009), pp. 9-14, Sesimbra, Lisbon, Portugal, June 2009.
  16. M. Agarwal et al., "Circuit Failure Prediction and Its Application to Transistor Aging," 25th IEEE VLSI Test Symposium, pp. 277-286, Berkeley, CA, USA, May 2007.
  17. M. Agarwal et al., "Optimized Circuit Failure Prediction for Aging: Practicality and Promise," IEEE International Test Conference (ITC 2008), pp. 1-10, Santa Clara, CA, USA, Oct. 2008.
  18. S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, "Adaptive Techniques for Overcoming Performance Degradation due to Aging in Digital Circuits," Asia and South Pacific Design Automation Conference (ASP-DAC 2009), pp. 284-289, Yokohama, Japan, Jan. 2009.
  19. Xiaoxiao Wang, et al., "Aging Adaption in Integrated Circuits Using a Novel Built-In Sensor," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, no. 1, pp. 109-121, Jan. 2015. https://doi.org/10.1109/TCAD.2014.2366876
  20. IEEE Standard Test Access Port and Boundary-Scan Architecture, IEEE std. 1149.1-2001, IEEE Computer Society.
  21. O. Khan and S. Kundu, "A Self-Adaptive System Architecture to Address Transistor Aging," Design, Automation & Test in Europe Conference & Exhibition (DATE '09), pp. 81-86, Nice, France, Apr. 2009.
  22. H. Yoon, T. Kang, and H. Yi, "A Design of FPGA Self-test Circuit Reusing FPGA Boundary Scan Chain," Journal of the Institute of Electronics and Information Engineers (IEIE), Vol. 52, No. 6, pp. 70-76, June 2015. https://doi.org/10.5573/ieie.2015.52.6.070