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A Design of Instruction Based Wrapped Core Linking Module for Hierarchical SoC Test Access  

Yi Hyun-Bean (한양대 공학대 컴퓨터공학과)
Park Sung-Ju (한양대 공학대 전자컴퓨터공학부)
Publication Information
The Transactions of the Korean Institute of Electrical Engineers D / v.52, no.3, 2003 , pp. 156-162 More about this Journal
Abstract
For a System-on-a-Chip(SoC) comprised of multiple IP cores, various design techniques have been proposed to provide diverse test link configurations. In this paper, we introduce a new instruction based Wrapped Core Linking Module(WCLM) that enables systematic integration of IEEE 1149.1 TAP'd cotes and P1500 wrapped cores with requiring least amount of area overhead compared with other state-of-art techniques. The design preserves compatibility with standards and scalability for hierarchical access.
Keywords
IEEE 1149.1; P1500;
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