Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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An Efficient SoC Test Architecture for Testing Various Cores in Parallel

다양한 코어의 병렬 테스트를 지원하는 효과적인 SOC 테스트 구조

  • Kim, Hyun-Sik (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Kim, Yong-Joon (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Park, Hyun-Tae (Department of Electrical and Electronic Engineering, Yonsei University) ;
  • Kang, Sung-Ho (Department of Electrical and Electronic Engineering, Yonsei University)
  • 김현식 (연세대학교 전기전자공학과) ;
  • 김용준 (연세대학교 전기전자공학과) ;
  • 박현태 (연세대학교 전기전자공학과) ;
  • 강성호 (연세대학교 전기전자공학과)
  • Published : 2006.10.25
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Abstract

In this paper, we present a new hardware architecture for testing various cores embedded in SoC. The conventional solutions need much testing time since only one core is tested at single test period. To enhance this, S-TAM, a novel test architecture, and its controller which enable parallel testing of various cores are proposed. S-TAM supports bus sharing to broadcast testing and cores to be tested are selected by using it. In addition, S-TAM controller enables the effective SoC test by simultaneous controlling the various test cores which are based on the different test architectures like IEEE 1149.1 and IEEE 1500.

본 논문은 SOC 내부의 다양한 코어들을 효율적으로 테스트하기 위한 하드웨어 구조에 초점을 두고 있다. 기존의 한 번에 한 개의 코어만을 순차적으로 테스트하는 방식은 많은 테스트 시간을 요구한다. 이를 보완하고자 본 논문에서는 병렬적으로 여러 코어를 테스트할 수 있는 S-TAM 구조 및 컨트롤러를 제안한다. S-TAM 구조는 테스트 버스 공유 방식을 이용하여 브로드캐스트 방법을 지원하며 이를 기반으로 하여 임의의 코어만을 선택적으로 테스트할 수도 있다. 이뿐 아니라 S-TAM 컨트롤러는 IEEE 1149.1 및 IEEE 1500 등과 같은 서로 상이한 테스트 기반을 통해 구현된 다양한 코어들을 동시에 제어함으로써 효과적인 SOC 테스트를 가능하게 한다.

Keywords

References

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