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Memory BIST Circuit Generator System Design Based on Fault Model  

Lee Jeong-Min (Department of Computing, Soongsil University)
Shim Eun-Sung (Department of Computing, Soongsil University)
Chang Hoon (Department of Computing, Soongsil University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.42, no.2, 2005 , pp. 49-56 More about this Journal
Abstract
In this paper, we propose a memory BIST Circuit Creation System which creates BIST circuit based on user defined fault model and generates the optimized march test algorithm. Traditional tools have some limit that regenerates BIST circuit after changing the memory type or test algorithm. However, this proposed creation system can automatically generate memory BIST circuit which is suitable in the various memory type and apply algorithm which is required by user. And it gets more efficient through optimizing algorithms for fault models which is selected randomly according to proposed nile. In addition, it support various address width and data and consider interface of IEEE 1149.1 circuit.
Keywords
BIST; Memory BIST; Embedded Memory; SRAM; Test;
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