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IEEE 1500 Wrapper and Test Control for Low-Cost SoC Test  

Yi, Hyun-Bean (Dept. of Computer Science & Engineering, Hanyang University)
Kim, Jin-Kyu (Dept. of Computer Science & Engineering, Hanyang University)
Jung, Tae-Jin (Dept. of Computer Science & Engineering, Hanyang University)
Park, Sung-Ju (Dept. of Electronical Engineering Computer Science, Hanyang Univ.)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.44, no.11, 2007 , pp. 65-73 More about this Journal
Abstract
This paper introduces design-for-test (DFT) techniques for low-cost system-on-chip (SoC) test. We present a Scan-Test method that controls IEEE 1500 wrapper thorough IEEE 1149.1 SoC TAP (Test Access Port) and design an at-speed test clock generator for delay fault test. Test cost can be reduced by using small number of test interface pins and on-chip test clock generator because we can use low-price automated test equipments (ATE). Experimental results evaluate the efficiency of the proposed method and show that the delay fault test of different cores running at different clocks test can be simultaneously achieved.
Keywords
Design for test; IEEE 1149.1; IEEE 1500; at-speed test; System-on-chip;
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