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An Efficient SoC Test Architecture for Testing Various Cores in Parallel  

Kim, Hyun-Sik (Department of Electrical and Electronic Engineering, Yonsei University)
Kim, Yong-Joon (Department of Electrical and Electronic Engineering, Yonsei University)
Park, Hyun-Tae (Department of Electrical and Electronic Engineering, Yonsei University)
Kang, Sung-Ho (Department of Electrical and Electronic Engineering, Yonsei University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.43, no.10, 2006 , pp. 140-150 More about this Journal
Abstract
In this paper, we present a new hardware architecture for testing various cores embedded in SoC. The conventional solutions need much testing time since only one core is tested at single test period. To enhance this, S-TAM, a novel test architecture, and its controller which enable parallel testing of various cores are proposed. S-TAM supports bus sharing to broadcast testing and cores to be tested are selected by using it. In addition, S-TAM controller enables the effective SoC test by simultaneous controlling the various test cores which are based on the different test architectures like IEEE 1149.1 and IEEE 1500.
Keywords
SoC; TAM; IEEE 1500; core test;
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